ESD Protection Apparatus Using Parasitic Capacitance Detection

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Solution Overview

Problem

Conventional power-rail ESD clamp circuits face challenges in distinguishing between ESD events and power-on conditions due to the RC time constant, leading to insufficient conduction during ESD events or mistriggering, and occupy a large layout area due to the use of capacitors and resistors.

Innovation Solution

An ESD protection apparatus utilizing the parasitic capacitance of an ESD clamp device as part of the detection mechanism, which reduces the layout area required and prevents mistriggering by generating a coupling potential to trigger a conduction signal for ESD between rail lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional RC detection circuit is used to control the conduction period of the clamp device, then the ESD protection capability can be controlled, but the layout area increases due to the capacitor and resistor

Engineering Contradiction:

ImproveESD protection capabilityVSAvoidlayout area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the detection function and clamp control function into a single integrated circuit block. The detection circuit directly controls the clamp device without requiring separate RC timing components, thereby reducing layout area while maintaining ESD protection capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The detection circuit is designed to perform multiple functions: detecting ESD events, controlling the conduction period of the clamp device, and generating the conduction signal. This multi-functional design eliminates the need for separate RC timing components, reducing the overall layout area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Area of stationary object

If the RC time constant is made small to reduce layout area, then the conduction period becomes insufficient, but the ESD protection capability is reduced

Engineering Contradiction:

Improvelayout areaVSAvoidconduction period

Core Design Contradiction:

Area of stationary objectVSDuration of action of moving object

Solution Approach 1:

The detection circuit dynamically adjusts the conduction period of the clamp device based on the detected ESD event characteristics. The circuit generates a conduction signal that maintains the clamp device in the on-state for the required duration to release ESD current, ensuring sufficient protection while using minimal layout area.

Inventive Principle:

Principle #15Dynamics

3Duration of action of moving object

If the RC time constant is made large to ensure sufficient conduction period, then the layout area increases, but the mistrigger risk increases under power-on conditions

Engineering Contradiction:

Improveconduction periodVSAvoidlayout area

Core Design Contradiction:

Duration of action of moving objectVSArea of stationary object

Solution Approach 1:

The detection circuit incorporates feedback mechanisms to monitor the ESD event characteristics and adjust the conduction signal accordingly. This feedback control ensures that the clamp device conducts for the appropriate duration without mistriggering during power-on conditions, while maintaining a compact layout.

Inventive Principle:

Principle #23Feedback

4Duration of action of moving object

If a conventional RC detection circuit is used, then the conduction period can be controlled, but the mistrigger risk increases under power-on conditions

Engineering Contradiction:

Improveconduction periodVSAvoidmistrigger resistance

Core Design Contradiction:

Duration of action of moving objectVSReliability

Solution Approach 1:

The detection circuit is designed to distinguish between ESD events and power-on conditions before generating a conduction signal. By implementing preliminary detection and discrimination logic, the circuit ensures that the clamp device only conducts during actual ESD events, preventing mistriggers during power-on while maintaining sufficient conduction period for ESD protection.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces the layout area and prevents mistriggering by utilizing innate parasitic capacitance for ESD detection, ensuring reliable ESD protection without additional capacitance devices and immune to transient-induced latch-up effects.

Implementation Method 1

utilizing a parasitic capacitance of an ESD clamp device as a part of an ESD detection mechanism

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS8654492B2Electrostatic discharge protection apparatus and method therefor

Publication Date: 2014.02.18 IND TECH RES INST

AI summary

An electrostatic discharge (ESD) protection apparatus includes a clamp circuit, a detection circuit and a control circuit. The clamp circuit has a first terminal and a second terminal respectively coupled to a first rail line and a second rail line. In response to an ESD event, the clamp circuit generates a first coupling potential at its coupling terminal. The detection circuit, coupled to the coupling terminal of the clamp circuit and the second rail line, outputs a detection signal in response to the first coupling potential. The control circuit, coupled to the first and second rail lines, the detection circuit and the clamp circuit, outputs a conduction signal to a control terminal of the clamp circuit in response to the detection signal. The clamp circuit is conducted in response to the conduction signal so that ESD between the first and second rail lines is performed through the clamp circuit.