ESD Power Clamp With Digitally Timed Latch
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Solution Overview
Problem
Existing power clamps are inefficient in terms of space usage and unable to handle fast power supply ramp times due to the requirement for large resistors and capacitors to achieve a 1 μs time constant, making them unsuitable for protecting devices from electrostatic discharge (ESD) events with rapid energy buildup.
Innovation Solution
A space-efficient ESD power clamp with a digitally timed latch is implemented, utilizing a trigger circuit with an RC network and an inverter stage, coupled with a timing circuit that controls a clamp transistor to prevent capacitor charging during ESD events, allowing for a smaller RC delay and faster power supply ramp times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large resistors and capacitors are used to achieve a 1 μs time constant, then the power clamp can detect ESD events, but the footprint of the protection circuit becomes large
Solution Approach 1:
The protection circuit is segmented into two functional parts: a small RC network for ESD detection and a digital timing circuit for power supply monitoring. The RC network uses minimal components (small R and C values) to detect ESD events, while the digital timing circuit separately handles power supply ramp time validation. This segmentation allows the RC network to be compact while maintaining ESD detection capability.
Solution Approach 2:
A digital timing circuit acts as an intermediary between the RC network and the clamp transistor control. The timing circuit receives the ESD detection signal from the RC network and validates whether the power supply ramp time is sufficient before enabling the clamp transistor. This intermediary function allows the use of smaller RC components while maintaining proper protection operation.
2Speed
If the RC time constant is made short to enable fast power supply ramp times, then the power clamp responds faster, but the ESD detection sensitivity decreases
Solution Approach 1:
The detection function is separated from the timing function. The RC network is optimized for ESD detection with appropriate time constant, while a separate digital timing circuit validates power supply ramp times. This allows the RC network to maintain detection sensitivity without being constrained by power supply ramp time requirements.
Solution Approach 2:
The circuit transitions from using a single RC time constant to control both ESD detection and power supply ramp timing to using two separate parameters: RC network time constant for ESD detection and digital timer setting for power supply ramp validation. This parameter separation allows independent optimization of both functions.
3Device complexity
If the RC network is used to control the clamp transistor, then the circuit is simple, but it cannot prevent false triggering during power supply ramp
Solution Approach 1:
A digital timing circuit serves as an intermediary gate between the RC network detection signal and the clamp transistor activation. The timing circuit validates whether the power supply has stabilized before allowing the clamp transistor to respond to ESD detection signals. This prevents false triggering during power supply ramps while maintaining relative circuit simplicity.
Solution Approach 2:
The digital timing circuit performs preliminary validation of the power supply state before enabling the clamp transistor response. By checking power supply stability in advance, the circuit prevents false triggering during ramp phases while maintaining readiness for legitimate ESD events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the footprint of the protection circuit, enhances sensitivity to noise, and enables effective protection during fast power supply ramp times by using a timing circuit to control the power clamp, rather than relying solely on the RC network, thereby improving the overall efficiency and reliability of ESD protection.
Implementation Method 1
the capacitor in the RC network from charging when the timing circuit is initiated
Data Source
AI summary
Embodiments include a system, apparatus, and method for ESD power clamps. Aspects include protecting a circuit using an ESD power clamp device. The ESD power clamp device includes a trigger circuit having a resistor-capacitor network and an inverter stage circuit, wherein the trigger circuit is configured to detect an ESD event. Aspects of the invention further include a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit controls the timing controlled transistor to prevent the capacitor in the RC network from charging when the timing circuit is initiated. Aspects also include a clamp transistor coupled to the trigger circuit, wherein the clamp transistor is controlled by a signal received from the trigger circuit, and a timing controlled transistor coupled to the trigger circuit and the timing circuit, where the timing controlled transistor switches states based on the output of the timing circuit.