ESD Power Clamp Circuit with Multi-Timing Networks
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Solution Overview
Problem
Conventional transient power clamps in integrated circuits (ICs) often interfere with normal operation, leading to false activation and damage due to their inability to distinguish between ESD events and power-on events, especially at high frequencies, and are unsuitable for technologies using PMOS devices.
Innovation Solution
A power clamp circuit with at least three independent timing networks and NMOS transistors that decouples clamp engagement, disengagement, and power-up detection, allowing for sub-microsecond power-up times and immunity to false triggering, enabling operation from high-voltage power rails without the need for PMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional transient power clamp with a single timing network is used, then ESD protection is provided, but false activation occurs during power-up and normal operation due to inability to distinguish ESD events from power-on events
Solution Approach 1:
The patent divides the single timing network into three independent timing networks with different time constants, each responsible for different detection functions. This segmentation allows the circuit to distinguish between ESD events and normal power-up/operation by comparing transient characteristics across multiple time scales, thereby eliminating false activation while maintaining ESD protection.
2Reliability
If a conventional transient power clamp with RC trigger circuit is used, then voltage rise is limited during ESD events, but power-up time is restricted due to minimum activation time requirements
Solution Approach 1:
The patent employs three timing networks with different time constants that dynamically respond to transient characteristics. The first timing network with a short time constant enables fast response to ESD events, while the second and third networks with longer time constants provide discrimination against power-up transients. This dynamic multi-time-constant approach allows sub-microsecond power-up times while maintaining effective voltage limiting during actual ESD events.
3Reliability
If a conventional transient power clamp using PMOS devices is used, then ESD protection is provided, but the design cannot be used in technologies with lower voltage rated PMOS devices
Solution Approach 1:
The patent changes the voltage rating parameter of the power clamp devices from PMOS (lower voltage rated) to NMOS (higher voltage rated). This parameter change enables the power clamp to operate from high-voltage power rails and be compatible with technologies that use lower voltage rated PMOS devices, while still providing effective ESD protection through the multi-time-constant timing networks.
4Reliability
If a conventional transient power clamp is used, then ESD protection is provided, but the circuit size is larger due to single timing network design
Solution Approach 1:
The patent segments the timing function into three independent networks with different time constants, each optimized for specific detection purposes. This segmentation enables more efficient use of circuit area by allowing parallel implementation of specialized detection functions rather than using a single large timing network, thereby reducing overall circuit area while maintaining comprehensive ESD protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides enhanced immunity to false activation, reduced power-up time, and smaller size, while effectively protecting ICs from ESD events without interfering with core circuitry, and supports operation from high-voltage power rails.
Implementation Method 1
The first timing network is connected between first and second voltage supply nodes and has a first time constant associated therewith, the first timing network being configured to detect a voltage transient between the first and second voltage supply nodes having a rise time less than or equal to a value of the first time constant.
Implementation Method 2
An ESD event involves charge transfer between the device and an external body due to electrostatic potential difference. During an ESD event, large currents can pass through the pins of an IC for very short durations of time causing electrical and thermal overstress
Data Source
AI summary
An ESD power clamp circuit includes first, second and third timing networks, first and second NMOS transistors and an enable circuit. The first timing network has a first time constant and detects a voltage transient between first and second voltage supply nodes having a rise time less than the first time constant. The first NMOS transistor has a gate connected with an output of the first timing network and a source connected with a gate of the second NMOS transistor. The second NMOS transistor has a drain connected with the first voltage supply node and a source connected with the second voltage supply node. The second timing network is coupled with the gate of the second NMOS transistor and has a second time constant that is greater than a duration of an ESD event. The third timing network is coupled with the enable circuit and has a third time constant, the third timing network generating a first control signal based on the third time constant. The enable circuit inhibits clamping action of the clamp circuit based on the first control signal.