ESD Protect Block for Transmit IC Using Reverse-Biased Diodes
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Solution Overview
Problem
CMOS power amplifier integrated circuits in packages without bond wires require effective ESD protection that minimizes signal distortion and chip area usage, as direct coupling of ESD clamp circuits can introduce significant capacitive loads and voltage drops, compromising both signal transmission and protection.
Innovation Solution
An ESD protect block is implemented between the input/output pad and the ESD clamp circuit, utilizing diodes and capacitors to reverse bias the diodes and buffer the transmit circuit from capacitive loads, preventing ESD clamp activation during high peak voltages, thereby ensuring minimal signal distortion and efficient protection with reduced chip area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an ESD clamp circuit is directly coupled to the PA output node, then ESD protection is provided, but the capacitive load of the ESD clamp circuit distorts the high frequency transmit signal
Solution Approach 1:
A transmission gate is introduced as an intermediary component between the ESD clamp circuit and the PA output node. The transmission gate acts as a controlled switch that isolates the ESD clamp circuit's capacitance from the high frequency transmit signal while allowing ESD current to pass through during discharge events, thereby eliminating signal distortion while maintaining protection functionality
2Object-generated harmful factors
If an on-chip inductor is used to isolate the ESD clamp circuit's capacitance, then signal transmission performance is improved, but significant chip area is required and voltage drop during ESD events compromises protection
Solution Approach 1:
The patent extracts the isolation function from a traditional inductor and implements it using a transmission gate based on MOS transistors. This replaces the bulky inductive structure with a compact transistor-based switch that provides the same isolation functionality without requiring significant chip area, while also avoiding the voltage drop issue associated with inductive structures during ESD events
3Reliability
If an on-chip inductor is used to isolate the ESD clamp circuit, then capacitance isolation is achieved, but resistance of the inductor causes voltage drop during ESD events compromising protection level
Solution Approach 1:
The transmission gate serves as an intermediary that provides a low-resistance path for ESD current while isolating the ESD clamp capacitance during normal operation. The MOS transistor structure of the transmission gate offers much lower resistance compared to an on-chip inductor, minimizing voltage drop during ESD events while maintaining effective capacitance isolation during signal transmission
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively isolates the ESD clamp circuit's capacitance from the power amplifier, maintaining high-performance signal transmission while providing adequate ESD protection, even at high voltage levels, with minimal impact on die area and signal integrity.
Implementation Method 1
one or more capacitors within the ESD protect block may charge up to various levels near the peak transmit voltage
Implementation Method 2
which reverse biases one or more diodes in the ESD protect block, thereby buffering the transmit circuit from the capacitive load of the ESD clamp circuit
Data Source
AI summary
An apparatus and method for providing electrostatic discharge protection of a transmit integrated circuit including an ESD protect block coupled to an integrated circuit pad in a package without bond wires, and an ESD clamp circuit coupled between the ESD protect block and ground. During transmission, one or more capacitors within the ESD protect block may charge up to various levels near the peak transmit voltage, which reverse biases one or more diodes in the ESD protect block, thereby buffering the transmit circuit from the capacitive load of the ESD clamp circuit. The ESD protect block may prevent the ESD clamp circuit from activating due to the high peak voltages output from the transmit circuit. An embodiment of the ESD protect block may apply particularly to transmit power amplifier circuits in which the output signal peaks at twice the supply voltage. In one embodiment applicable for lower voltage CMOS processes, the ESD protect block includes a diode and a capacitor. In another embodiment applicable for higher voltage CMOS processes, the ESD protect block includes two diodes, one or two capacitors, and an optional resistor.