ESD Protection Device Structure Using Vertical and Lateral BJTs
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Solution Overview
Problem
Existing ESD protection devices in semiconductor ICs face challenges in maintaining effective protection as device scaling reduces gate oxide layer breakdown voltages, leading to potential damage from high ESD currents.
Innovation Solution
The ESD protection device structure incorporates a well with doped regions of different conductive types to form vertical and lateral BJTs, with a second doped region implanted into the first heavy doped region and drift region to increase secondary breakdown current and reduce trigger voltage, creating a low impedance path for ESD current discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate oxide layer thickness is reduced to scale down device dimensions, then device integration density is improved, but breakdown voltage decreases making the gate oxide layer more susceptible to ESD damage
Solution Approach 1:
The patent introduces a parasitic bipolar transistor structure as an intermediary protection mechanism. The bipolar transistor (formed by doped regions in the drift region) acts as a mediator that diverts ESD current away from the gate oxide layer through its collector-emitter path, protecting the scaled-down device while maintaining high integration density
Solution Approach 2:
The patent modifies the electrical parameters of the drift region by introducing specific doped regions with different conductivity types. This changes the breakdown characteristics and current distribution in the ESD protection path, enabling the device to handle higher ESD currents without damaging the thin gate oxide layer
2Reliability
If prior-art ESD protection devices using parasitic bipolar transistors are used in ND and PS modes, then ESD protection function is provided, but the high turned-on voltage causes gate oxide layer burnout due to high ESD current
Solution Approach 1:
The patent applies local quality by creating specific doped regions with different conductivity types in particular locations within the drift region. These localized doped regions form the bipolar transistor structure that provides controlled ESD current paths, protecting specific areas from high current damage while maintaining overall device functionality
Solution Approach 2:
The patent converts the potentially harmful high ESD current into a beneficial protective mechanism by utilizing the bipolar transistor's current amplification effect. The ESD current triggers the bipolar transistor to activate, creating a low-impedance discharge path that safely dissipates the energy that would otherwise damage the gate oxide layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the ESD protection device's ability to tolerate higher ESD pulses, meeting industry specifications by increasing secondary breakdown current and reducing trigger voltage, while minimizing power consumption and impedance.
Implementation Method 1
The present invention implants the second doped region having different conductive type from the first doped region into the first heavy doped region and the first drift region
Data Source
AI summary
An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised.