ESD Protection Device Buried Layer Reduces Parasitic Capacitance
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Solution Overview
Problem
Existing ESD protection devices for high-speed data transfer interfaces face challenges in achieving both high ESD protection performance and low parasitic capacitance, as the doping concentration of epitaxial layers is affected by self-doping effects, leading to increased capacitance values that do not meet the required standards.
Innovation Solution
A semiconductor structure is developed with a buried layer of a first doping type and a buried layer of a second doping type, where the epitaxial layer is formed with a second doping type, counteracting self-doping effects to reduce parasitic capacitance, and a metal layer connects doped regions to form electrodes, optimizing doping concentrations within specific ranges to achieve ultra-low capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the doping concentration of the epitaxial layer is increased to improve ESD protection performance, then the ESD protection capability is enhanced, but the parasitic capacitance increases and exceeds the required limit
Solution Approach 1:
The patent introduces a buried layer with opposite doping type between the epitaxial layer and substrate, changing the doping parameter distribution to counteract self-doping effects and reduce parasitic capacitance while maintaining ESD protection performance
Solution Approach 2:
The buried layer acts as an intermediary element that mediates between the epitaxial layer and substrate, preventing direct harmful self-doping interaction and enabling capacitance reduction without sacrificing protection capability
2Reliability
If the junction area of the PN junction is increased to improve ESD protection performance, then the voltage clamping capability is enhanced, but the parasitic capacitance increases
Solution Approach 1:
The patent modifies the doping concentration parameter through the buried layer to decouple the relationship between junction area and capacitance, allowing larger junction areas for better clamping without proportional capacitance increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance, ensuring ESD protection devices meet the requirements for high-speed interfaces by carefully managing doping concentrations and self-doping effects, resulting in enhanced ESD protection performance.
Implementation Method 1
due to self-doping of the buried layer NBL, the doping concentration of the region (indicated by a dashed box in FIG. 3) where the epitaxial layer N− is close to the heavily doped substrate P+sub will be increased
Data Source
AI summary
Disclosed are a semiconductor structure of an ESD protection device with low capacitance and a method for manufacturing the same. The method for manufacturing a semiconductor structure of an ESD protection device, comprising: forming a buried layer with a first doping type and a buried layer with a second doping type in a first region and a second region at a top surface of a semiconductor substrate with a first doping type, respectively; forming an epitaxial layer with a second doping type on the buried layer with the first doping type and the buried layer with the second doping type, wherein the buried layer with the first doping type and the buried layer with the second doping type are buried between the semiconductor substrate and the epitaxial layer, a first doped region with a first doping type is formed at a top of a third region on the buried layer with the second doping type located on the epitaxial layer.