ESD Protection Circuit with RC Triggered Back-Gate Biasing
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Solution Overview
Problem
Existing ESD protection circuits face a trade-off between reducing power consumption and maintaining discharge performance, as increasing driving force leads to higher leakage current and power consumption, while limiting leakage current compromises discharge performance and may damage the shunt transistor.
Innovation Solution
The ESD protection circuit incorporates a diode connected between the power-supply lines, a shunt MOS transistor, and an RC trigger circuit, where the back gate of the MOS transistor is connected to a node between a capacitor and resistor, allowing the well region potential to vary and apply a forward voltage to the p-n junction, enhancing the driving force and discharge performance while controlling leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the driving force of the shunt MOS transistor is increased to improve discharge performance, then the discharge performance is improved, but the leakage current increases and power consumption increases
Solution Approach 1:
The invention dynamically adjusts the driving force of the shunt MOS transistor by applying a variable voltage to the well region through the RC trigger circuit. During ESD events, the circuit provides high driving force for effective discharge, while during normal operation, the driving force is reduced to minimize leakage current, thus resolving the contradiction between discharge performance and power consumption
Solution Approach 2:
The invention changes the electrical parameters (voltage potential) of the well region connected to the MOS transistor based on operating conditions. By varying the well region potential through the RC trigger circuit, the transistor's driving force and leakage characteristics are adjusted dynamically, allowing optimization of both discharge performance and power consumption
2Use of energy by moving object
If the leakage current is limited to reduce power consumption, then the power consumption is reduced, but the driving power for the shunt transistor drops and discharge performance is lowered
Solution Approach 1:
The circuit dynamically switches between low-power mode and high-performance mode by adjusting the well region voltage through the RC trigger circuit. During normal operation, limited leakage current reduces power consumption, while during ESD detection, the circuit rapidly increases driving power to ensure adequate discharge performance, thus resolving the contradiction
3Reliability
If the driving force of the shunt transistor is increased to improve discharge performance, then the discharge performance is improved, but the shunt transistor may be damaged during operation due to excessive current
Solution Approach 1:
The RC trigger circuit acts as a cushioning mechanism that detects voltage surges beforehand and prepares the well region voltage to gradually increase the driving force. This prevents sudden excessive current spikes that could damage the transistor while still providing adequate discharge performance, thus resolving the contradiction between performance and durability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the discharge performance of the ESD protection circuit by increasing the driving force of the shunt transistor and reducing overshoot, thereby preventing damage to the transistor while minimizing power consumption.
Implementation Method 1
The RC trigger circuit generates a trigger signal at a junction between a series connected resistor and a capacitor
Implementation Method 2
An ESD protection circuit is used to protect an internal circuit of a semiconductor device against surges generated when an ESD occurs
Implementation Method 3
A potential of the connection point varies so that a forward voltage is applied to a p-n junction between the well region and the source of the MOS transistor to correspond with the surge
Data Source
AI summary
An ESD protection circuit has a diode that includes an anode connected to a first power-supply line and a cathode connected to a second power-supply line. A metal-oxide-semiconductor (MOS) transistor is connected in series with the diode. A trigger circuit is configured to output a trigger signal to a gate of the MOS transistor in synchronization with a surge on the first power-supply line. A first resistor and a first capacitor are connected in series between the first power-supply line and the second power-supply line. A well region, in which the source and the drain of the MOS transistor are disposed, is connected to a connection point between the first resistor and the first capacitor. A potential of the connection point varies so that a forward voltage is applied to a p-n junction between the well region and the source of the MOS transistor to correspond with the surge.