ESD Protection Circuit Cell for Multi-Power Domain ICs
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Solution Overview
Problem
Integrated circuits (ICs) with advanced sub-quarter-micron CMOS technologies are increasingly susceptible to damage from electrostatic discharge (ESD) due to shallower junction depths, thinner gate oxides, and other design features, which can lead to ESD current flowing through damaging paths, causing transistor damage, especially in multi-power domain circuitry.
Innovation Solution
An ESD protection circuit is designed as a standard cell for ICs, incorporating a pair of clamping diodes or alternative devices like gate-Vdd PMOS and grounded gate NMOS, arranged to safely divert ESD current to ground, ensuring the gates of transistors are not exposed to high ESD voltage, and can be easily integrated into IC designs with flexible layout options to save area and enhance protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If advanced sub-quarter-micron CMOS technologies are used to miniaturize IC devices, then device integration and scaling are improved, but susceptibility to ESD damage increases due to shallower junction depths and thinner gate oxides
Solution Approach 1:
The patent introduces an ESD protection circuit as an intermediary component between the ESD threat and the sensitive CMOS devices. This protection circuit acts as a mediator that intercepts and safely dissipates ESD energy before it can reach and damage the thin-gate-dielectric MOS transistors, thus resolving the contradiction between device miniaturization and ESD susceptibility
Solution Approach 2:
The ESD protection circuit is designed to provide beforehand cushioning by being pre-configured to absorb and divert ESD current before it can cause damage. The circuit includes components specifically positioned and configured to cushion the impact of ESD events, protecting the vulnerable miniaturized devices in advance
2Reliability
If diode module is connected to I/O ground bus between two power domains, then ESD current diversion path is provided, but ESD current may flow through damaging paths other than the I/O ground bus, damaging thin-gate-dielectric MOS transistors
Solution Approach 1:
The patent applies local quality by providing ESD protection specifically at the vulnerable input node where the ESD current enters, rather than relying solely on a general diode module connected to the I/O ground bus. The protection circuit is locally positioned and configured to address the specific vulnerability of the thin-gate-dielectric MOS transistors at the input interface
Solution Approach 2:
The ESD protection function is segmented into a dedicated protection circuit that is separate from the main signal path and power domain interface. This segmentation allows the protection circuit to specifically handle ESD current diversion without interfering with normal multi-power domain operations, preventing ESD current from flowing through damaging paths
3Quantity of substance
If larger capacitance IC packages are used, then package capability is improved, but discharge peak current levels increase, creating new ESD protection challenges
Solution Approach 1:
The patent addresses the increased discharge peak current from larger capacitance packages by modifying the protection circuit parameters. The protection circuit is designed with components and configurations that can handle higher current levels, adjusting the protection parameters to match the increased stress from larger package capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ESD protection circuit effectively safeguards ICs from ESD damage by safely routing ESD current, reducing the risk of transistor damage and allowing for more efficient use of IC space, thereby enhancing the reliability and performance of ICs in multi-power domain environments.
Implementation Method 1
electrostatic discharge ('ESD') protection for integrated circuits
Implementation Method 2
incorporating a pair of clamping diodes or alternative devices like gate-Vdd PMOS and grounded gate NMOS, arranged to safely divert ESD current to ground
Data Source
AI summary
A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.