ESD Protection Circuit with External Detection
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Solution Overview
Problem
The existing ESD protection circuits for integrated circuits require a large number of capacitors and resistors, which occupy significant area and limit the size of the chip as the number of power sources increases, making it essential to reduce the number of these components.
Innovation Solution
An ESD protection circuit with an ESD detection circuit disposed outside the power clamp circuits, using trigger units and power clamp circuits connected to the power sources to detect and discharge electrostatic charges, reducing the need for multiple capacitors and resistors within the power clamp circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of power sources is increased to provide more functionality, then the versatility of the integrated circuit is improved, but the number of capacitors and resistors required for ESD protection increases, occupying more chip area
Solution Approach 1:
The patent merges the ESD detection function into the existing power clamp circuit structure by utilizing the gate terminals of the NMOS transistors as detection nodes. The capacitors and resistors that were previously dedicated solely to ESD detection are now shared between ESD detection and power management functions, eliminating the need for separate detection circuitry and reducing overall component count.
Solution Approach 2:
The capacitors and resistors in the power clamp circuit are designed to serve dual purposes: they function as power management components during normal operation and as ESD detection components during electrostatic discharge events. This multi-functionality allows the circuit to provide both power regulation and ESD protection without requiring additional dedicated components for each function.
2Reliability
If separate ESD detection circuits are added to each power clamp circuit, then the ESD protection reliability is improved, but the device complexity and component count increase
Solution Approach 1:
The patent combines the ESD detection function with the power clamp circuit by using the existing transistor gates as detection elements. The capacitors connected to the gates serve both as coupling elements for power management and as detection elements for ESD events, eliminating the need for separate detection circuits while maintaining comprehensive ESD protection across all power sources.
3Measurement precision
If capacitors and resistors are placed within each power clamp circuit for ESD detection, then the ESD detection precision is improved, but the area occupied by these components increases
Solution Approach 1:
The patent merges the ESD detection function into the existing power clamp circuit structure by utilizing the gate terminals of the NMOS transistors as detection nodes. The capacitors and resistors that were previously dedicated solely to ESD detection are now shared between ESD detection and power management functions, eliminating the need for separate detection circuitry and reducing overall component count.
Solution Approach 2:
The capacitors and resistors in the power clamp circuit are designed to serve dual purposes: they function as power management components during normal operation and as ESD detection components during electrostatic discharge events. This multi-functionality allows the circuit to provide both power regulation and ESD protection without requiring additional dedicated components for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for effective protection of integrated circuits from electrostatic discharge without increasing the chip size, as the ESD detection circuit is external to the power clamp circuits, thereby minimizing the area occupied by capacitors and resistors.
Implementation Method 1
a RC circuit composed of the capacitor 16 and the resistor 18 can provide a high voltage potential to the gate of the first NMOS transistor 20
Implementation Method 2
the electrostatic charges occurring in the high power line 10a can flow through the first NMOS transistor 20 to trigger on the second NMOS transistor 22
Data Source
AI summary
The present invention provides an electrostatic discharge (ESD) protection circuit including an ESD detection circuit and a plurality of power clamp circuits. The ESD detection circuit is electrically connected to a first high power line, a second high power line and at least one low power line, and is used to detect an ESD event occurring in the first high power line and another ESD event occurring in the second high power line. The ESD detection circuit includes a first trigger unit and a second trigger unit, electrically connected to the first high power line and the second high power line respectively. Each power clamp circuit has a trigger node, and the trigger nodes are electrically connected to the first trigger unit and the second trigger unit.