ESD Protection Circuit with EOS Immunity via Cross Voltage Control
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Solution Overview
Problem
Conventional ESD protection circuits are vulnerable to damage from Electrical Over-Stress (EOS) due to their inability to differentiate between Electro-Static Discharge (ESD) and EOS events, leading to erroneous triggering and subsequent damage from sustained high currents during EOS.
Innovation Solution
An ESD protection circuit with EOS immunity is designed, featuring a first connection circuit, an EOS control circuit, and an ESD clamp that operates in triggered and reverse conduction modes. The EOS control circuit provides a cross voltage to prevent the ESD clamp from conducting during EOS, thereby increasing the equivalent resistance and preventing damage from excessive voltage and current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ESD clamp conducts a current path during EOS, then ESD protection is provided, but the ESD protection circuit is damaged by sustained exceeding current
Solution Approach 1:
The circuit changes the conduction state of the ESD clamp based on voltage parameters. During ESD events, the clamp conducts to provide protection. During EOS events, when voltage exceeds a threshold, the EOS control circuit activates to prevent sustained conduction, thereby changing the parameter of current flow from continuous to blocked, preventing damage while maintaining protection capability
Solution Approach 2:
The EOS control circuit acts as an intermediary between the pad and the ESD clamp. It monitors the voltage conditions and controls the conduction state of the ESD clamp, serving as a mediator that prevents harmful sustained current during EOS while allowing protective current flow during ESD events
2Reliability
If the ESD protection circuit provides a current path for ESD, then ESD charges are dissipated, but the circuit cannot differentiate between ESD and EOS events
Solution Approach 1:
The EOS control circuit implements feedback by continuously monitoring the voltage at the pad and adjusting the conduction state of the ESD clamp accordingly. When the monitored voltage indicates an EOS condition (sustained high voltage), the feedback mechanism activates to block the current path, whereas during ESD (rapid voltage spike), the feedback allows conduction, thus achieving event differentiation
Solution Approach 2:
The circuit dynamically adjusts its behavior based on the temporal characteristics of the input event. The ESD clamp transitions between conducting and non-conducting states based on real-time voltage conditions controlled by the EOS control circuit, enabling the system to adapt its protection mechanism to the specific type of electrical stress encountered
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively protects internal chip circuits from both ESD and EOS by dissipating ESD charges quickly and maintaining high resistance during EOS, preventing damage from sustained high currents.
Implementation Method 1
ESD (Electro-Static Discharge) happens when accumulated electro-static charges are suddenly conducted to conductive structures of the I/O interfaces
Implementation Method 2
the invention provides an ESD protection circuits with EOS immunity which not only provides a current path dissipating charges during ESD, but also greatly increases equivalent resistance of the current path during EOS
Data Source
AI summary
ESD protection circuit with EOS immunity is provided, which includes a first connection circuit, a first EOS control circuit formed by at least a diode, and an ESD clamp respectively coupled between a pad, a first clamp node, an I/O clamp node and a second source node. When the ESD clamp detects ESD through the I/O clamp node, it is triggered to conduct from the I/O clamp node to the second source node. When the pad receives EOS, the first EOS control circuit provides a cross voltage between the first clamp node and the I/O clamp node, such that a voltage of the I/O clamp node becomes less than a characteristic voltage of the ESD clamp to prevent the ESD clamp from reverse conducting.