ESD Protection Circuit Segmentation for Multi-Chip Package Power Optimization
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Solution Overview
Problem
Multi-chip packages face significant power consumption due to parasitic capacitance from conventional ESD protection circuitry, which is not necessary during normal operation, especially for die-to-die connections that are not exposed to external ESD events.
Innovation Solution
Implementing switches to control and disable ESD protection circuits during fabrication and testing, and reducing the size or removing HBM type ESD protection from die-to-die connections in packaged devices, while maintaining minimal secondary CDM type protection for operational safety, thereby reducing parasitic capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits are used on all contacts, then chip reliability during fabrication and operation is improved, but power consumption increases due to parasitic capacitance
Solution Approach 1:
The patent segments ESD protection into two distinct circuits: a first ESD protection circuit for fabrication/testing contacts and a second ESD protection circuit for operational contacts. This segmentation allows each circuit to be optimized for its specific function, reducing overall parasitic capacitance while maintaining comprehensive protection where needed.
Solution Approach 2:
The patent implements dynamic control of ESD protection circuits through test mode signals. During fabrication and testing, the first ESD protection circuit is activated; during normal operation, it is deactivated and replaced by the second ESD protection circuit. This dynamic switching reduces parasitic capacitance in operational mode while maintaining protection during vulnerable fabrication stages.
2Reliability
If ESD protection circuits are maintained on die-to-die connections, then protection against ESD events is improved, but power consumption increases due to unnecessary protection during operation
Solution Approach 1:
The patent applies dynamic control to die-to-die connection ESD protection by using test mode signals to activate/deactivate the first ESD protection circuit. During operational mode, the first ESD protection circuit is deactivated, reducing parasitic capacitance on die-to-die connections. The second ESD protection circuit remains active to provide necessary protection for external contacts.
Solution Approach 2:
The patent applies different ESD protection strategies to different locations: the first ESD protection circuit protects fabrication/test contacts and die-to-die connections during manufacturing, while the second ESD protection circuit protects external package contacts during operation. This localized approach ensures protection where needed while minimizing parasitic capacitance elsewhere.
3Use of energy by moving object
If minimal ESD protection is used during operation, then power consumption is reduced, but protection capability during fabrication and testing is compromised
Solution Approach 1:
The patent uses dynamic switching based on test mode signals to activate the first ESD protection circuit during fabrication and testing, then deactivate it in favor of the second circuit during operation. This ensures strong protection during vulnerable manufacturing stages while minimizing parasitic capacitance during operational mode.
Solution Approach 2:
The first ESD protection circuit is designed and activated in advance during fabrication and testing stages, providing necessary protection before the chip is packaged. The second ESD protection circuit is then activated for operational contacts after packaging, ensuring protection is available at each appropriate stage without unnecessary parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power consumption in multi-chip packages by minimizing unnecessary ESD protection during operation, increasing the operational time of portable devices without compromising device yield or safety.
Implementation Method 1
ESD occurs when there is a voltage difference between the chip and another object that is brought into contact with the chip. The voltage difference results in a high voltage discharge that damages the circuits on the chip.
Implementation Method 2
Paired diodes 21 comprise the ESD circuit that is used to shunt a voltage discharge.
Data Source
AI summary
Power consumption of electronic components is reduced, particularly in a multi-chip package. Embodiments reduce parasitic capacitance of a semiconductor chip by reducing ESD protection circuitry that is not needed during operation of the package. ESD protection circuitry would be operational during production and/or testing of the chip, but some circuitry would be disabled or removed prior to normal operation of the multi-chip package.