ESD Protection Circuit for Semiconductor IC
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Solution Overview
Problem
Complementary metal-oxide-semiconductor (CMOS) IC devices are vulnerable to electrostatic discharge (ESD) due to their small gate oxide film, leading to potential damage from thermal breakdown, metal contact fusion, and insulation breakdown, and existing ESD protection circuits are large, consuming excessive current and failing to operate reliably at low immunity levels.
Innovation Solution
A semiconductor device with a protection circuit that includes a multi-stage arrangement of grounded gate NMOSs connected in parallel, a high-voltage transistor, and a resistor between the gates and ground, or a silicon controlled rectifier (SCR) with a high-voltage transistor, which forms a discharge path and disconnects the pad and internal circuit during ESD, operating at a voltage lower than the junction breakdown voltage and occupying a smaller area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large number of GGNMOSs are arranged in parallel to ensure ESD protection operation, then ESD protection reliability is improved, but the circuit area and parasitic components increase
Solution Approach 1:
The patent merges multiple GGNMOS transistors into a single unified structure where eight to ten GGNMOSs are combined in parallel between the pad and ground. This merging approach maintains the ESD protection functionality of multiple transistors while reducing the overall circuit area and minimizing parasitic components that would result from discrete parallel arrangements.
2Reliability
If multiple GGNMOSs are used in parallel to ensure all operate during ESD, then ESD protection coverage is improved, but current consumption increases due to bulk device operation
Solution Approach 1:
The patent applies local quality by configuring the GGNMOS transistors with their gates and sources connected to VSS via substrate (or well) and drains connected to pad 10. This specific connection configuration optimizes the local electrical characteristics of each transistor, enabling them to operate as surface devices with lower current consumption while maintaining comprehensive ESD protection coverage.
3Object-generated harmful factors
If GGNMOSs with lateral parasitic bipolar operations are used, then ESD discharge path is formed, but internal circuit may be shocked due to high voltage before junction breakdown
Solution Approach 1:
The patent introduces an intermediary protection mechanism by connecting the gates and sources of all GGNMOS transistors to VSS through the substrate (or well). This intermediary connection acts as a mediator that controls the activation of lateral parasitic bipolar operations, allowing ESD discharge while preventing excessive high voltage from reaching the internal circuit before junction breakdown occurs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides rapid and stable ESD protection for semiconductor IC devices, efficiently disconnecting the pad and internal circuit from ESD voltage, reducing the risk of damage and operating efficiently while minimizing area occupancy.
Implementation Method 1
ESD may occur when electrostatic charges are transferred between two objects having different electrostatic potentials
Implementation Method 2
impact ionization or avalanche may occur in a reverse-biased drain/substrate junction
Data Source
AI summary
Embodiments relate to a device for protecting a semiconductor IC device from an electrostatic discharge (ESD). According to embodiments, the device may have a rapid response speed and a stable operation against an ESD and may efficiently protect an internal circuit of a semiconductor IC from an ESD voltage lower than a junction breakdown voltage. According to embodiments, the device for protecting the semiconductor IC may include a pad, an internal circuit electrically connected to the pad, and a protection circuit which forms a discharge path between the pad and the internal circuit and disconnects the pad and the internal circuit, when an overvoltage due to an electrostatic discharge is applied to the pad.