ESD Protection Circuit With Single Trigger Control
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Solution Overview
Problem
Integrated circuits face challenges in providing effective electrostatic discharge (ESD) protection, particularly in maintaining compatibility with higher voltage requirements while minimizing silicon area and ensuring noise immunity, as existing solutions often require multiple trigger circuits or increased silicon area due to high resistance in clamp paths.
Innovation Solution
A high voltage tolerant ESD protection circuit is designed with a single trigger control circuit and a switchable current sinking circuit using series connected PMOS transistors, coupled with a voltage divider circuit to generate an intermediate voltage level, allowing the circuit to handle voltages exceeding the breakdown voltage of devices used, while minimizing silicon area by implementing all components in a single n-well.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple trigger circuits are used to provide high voltage tolerant ESD protection, then the ESD protection capability is improved, but the silicon area required increases
Solution Approach 1:
The patent combines multiple trigger circuits into a single integrated trigger circuit that can simultaneously detect voltage changes on multiple rails. This single trigger circuit uses a network of transistors to monitor both the 3.3V rail and 5V rail, generating a trigger signal when either rail experiences an ESD event, thereby reducing the total silicon area while maintaining comprehensive ESD protection capability.
Solution Approach 2:
The single trigger circuit is designed to perform multiple functions: it detects ESD events on both 3.3V and 5V rails, generates appropriate trigger signals for different voltage domains, and controls multiple clamp circuits simultaneously. This multi-functional design eliminates the need for separate trigger circuits for each voltage rail, reducing overall circuit complexity and silicon area.
2Reliability
If PMOS devices in separate n-wells are used for ESD protection, then the ESD protection coverage is improved, but the silicon area and resistance increase
Solution Approach 1:
The patent places multiple PMOS devices (specifically the ESD protection transistors) within a single shared n-well structure rather than using separate n-wells for each device. This consolidation reduces the total silicon area occupied by the ESD protection circuitry while maintaining adequate ESD protection coverage through proper transistor sizing and configuration within the shared well.
Solution Approach 2:
The patent optimizes the local electrical characteristics within the shared n-well by carefully designing the transistor dimensions, doping profiles, and interconnect structures to ensure that each PMOS device maintains its required ESD protection performance despite sharing the well with other devices. This localized optimization ensures that ESD protection coverage is not compromised by the area-reducing consolidation.
3Device complexity
If the clamp path resistance is increased to simplify circuit design, then the circuit complexity is reduced, but the ESD protection effectiveness deteriorates
Solution Approach 1:
The patent carefully optimizes the resistance values of components in the clamp path, including the selection of specific transistor dimensions and the addition of resistance compensation elements. By adjusting these parameters, the circuit achieves low enough clamp path resistance to effectively discharge ESD currents while maintaining a relatively simple overall circuit architecture that does not require complex active control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively sinks large currents during ESD events, maintaining low resistance and reducing silicon area requirements, ensuring robust ESD protection with backward compatibility and improved noise immunity.
Implementation Method 1
a voltage divider circuit configured to generate an intermediate voltage level at an intermediate node between the positive ESD clamp rail voltage and the negative ESD clamp rail voltage, thereby increasing the tolerance of the ESD protection circuit to voltages higher than the breakdown voltage of the devices used in the ESD protection circuit
Implementation Method 2
ESD many times originates from build up of static charge near the IC or on a human handling the IC, leading to extremely high voltages developed near the IC, and typically results in an electrical discharge of very high current for a short duration
Data Source
AI summary
In one embodiment, an ESD protection circuit comprises a switchable current sinking circuit connected to a positive ESD clamp rail voltage, which may be a power supply voltage, and a single trigger control circuit coupled to a control connection of the switchable current sinking circuit. The single trigger control circuit may be configured to couple the control connection of the switchable current sinking circuit to a negative ESD clamp rail voltage, which may be signal ground, during an ESD event occurring on the positive ESD clamp rail connection. In one embodiment, the switchable current sinking circuit is capable of sinking large amounts of current, and the ESD protection circuit is tolerant of rail voltages that exceed the breakdown voltage of semiconductor devices used in constructing the ESD circuit. In one embodiment, the single trigger control circuit is implemented with a single n-well, thereby minimizing the amount of required silicon area during fabrication of the ESD protection circuit.