Low Capacitance ESD Protection Circuit Structure
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Solution Overview
Problem
Conventional ESD protection circuits in integrated circuits face challenges with high capacitance, which disrupts signal integrity at high signal frequencies, making it difficult to protect devices from electrostatic discharges while maintaining circuit performance.
Innovation Solution
A low capacitance ESD protective circuit structure is designed using a semiconductor substrate with specific doping regions and spacings, including N well and P well regions, and diode configurations to minimize parasitic capacitance, allowing for effective ESD protection without substantial modification to existing processes or equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits are employed to divert power surges away from susceptible devices, then device protection against electrostatic discharge is improved, but the capacitance of the protective device becomes too high which disrupts signal integrity at high frequencies
Solution Approach 1:
The ESD protection circuit is segmented into multiple series-connected diode devices (first plurality between input/output pad and Vdd, second plurality between input/output pad and ground). This segmentation divides the total capacitance into smaller portions distributed across multiple devices, reducing the overall capacitance impact on high-frequency signals while maintaining ESD protection functionality through the series configuration.
Solution Approach 2:
The patent changes the electrical parameters of the ESD protective device by using heavily doped P+ and N+ regions to create diode structures with optimized junction capacitance. The doping concentrations and junction depths are specifically controlled to minimize parasitic capacitance, achieving a total capacitance of less than 0.1 pF between the input/output pad and both Vdd and ground, thereby preserving signal integrity at high frequencies.
2Productivity
If device size is reduced to increase circuit density, then the number of devices that can be fabricated on each wafer is improved, but the devices become more susceptible to harmful electrostatic discharges
Solution Approach 1:
The patent applies local quality by implementing ESD protection structures with specific doping characteristics (heavily doped P+ and N+ regions) at critical locations where ESD protection is needed, such as at the input/output pad interfaces. This localized approach provides targeted ESD protection without requiring proportional increases in overall device size, allowing small device geometries to maintain adequate protection while preserving high circuit density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a low capacitance of less than 0.1 pF, effectively protecting against electrostatic discharges while preserving signal integrity in high-frequency applications, enhancing the reliability of integrated circuits.
Implementation Method 1
conventional ESD protection circuits are employed to divert power surges away from susceptible devices to ground
Implementation Method 2
The first heavily doped N+ region is coupled to a Vdd potential of an internal circuit. A first spacing is disposed between the first heavily doped P+ region and the first heavily doped N+ region
Data Source
AI summary
An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.