ESD Protection Circuit for Thin Gate Insulation

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Solution Overview

Problem

Conventional ESD protection circuits fail to effectively protect the gate insulating layer of NMOS transistors in semiconductor devices due to high ESD onset voltage, leading to potential damage from excessive voltage before the protection circuit can operate.

Innovation Solution

An ESD protection circuit is designed with a first electrostatic protection unit connected to the power source supply pad, generating a driving voltage through a voltage-drop unit to discharge ESD current, and a second electrostatic protection unit driven by this voltage to reduce the voltage applied to the gate of the NMOS transistor, using a combination of transistors, diodes, and resistors to manage ESD current flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional NMOS transistor with gate connected to ground is used for ESD protection, then the protection circuit can discharge ESD current, but the ESD onset voltage becomes very high causing the gate insulating layer to break before protection operates

Engineering Contradiction:

ImproveESD protection capabilityVSAvoidgate insulating layer damage

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A driver circuit is introduced as an intermediary between the ESD protection transistor and the ground connection. The driver circuit includes a PMOS transistor and resistor that generate a negative gate voltage on the protection transistor, creating an intermediate control mechanism that lowers the ESD onset voltage without directly connecting the gate to ground, thus preventing gate insulating layer breakdown while maintaining protection capability

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate voltage parameter of the ESD protection transistor is changed from 0V (ground connection) to a negative voltage generated by the driver circuit. This parameter change reduces the ESD onset voltage, allowing the protection circuit to activate at lower voltages before the gate insulating layer can be damaged by excessive voltage

Inventive Principle:

Principle #35Parameter changes

2Productivity

If the gate insulating layer is made thinner to improve device performance, then device performance improves, but the destructive voltage threshold decreases making the circuit more susceptible to ESD damage

Engineering Contradiction:

Improvedevice performanceVSAvoidresistance to ESD damage

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The driver circuit performs preliminary action by pre-charging the gate of the ESD protection transistor to a negative voltage state before ESD occurs. This preliminary voltage setup ensures that when ESD strikes, the protection transistor activates at a lower voltage threshold, providing protection before the thin gate insulating layer can be damaged by high voltage

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution significantly reduces the ESD onset voltage, protecting the gate insulating layer by discharging ESD current before it reaches damaging levels, allowing for thinner gate insulating layers and improved semiconductor device performance.

Implementation Method 1

generates a first driving voltage by means of a voltage-drop unit thereby causing an ESD current to flow

Methodology Applied

Scientific EffectVoltage drop: Joule Heating

Implementation Method 2

the first electrostatic protection unit discharges an ESD current into the power source supply pad when an ESD is introduced into the input/output pad

Methodology Applied

Scientific EffectElectrostatic discharge: Electrostatic Discharge

Data Source

PatentUS7839613B2Electrostatic discharge protection circuit protecting thin gate insulation layers in a semiconductor device

Publication Date: 2010.11.23 MIMIRIP LLC

AI summary

An electrostatic discharge protection circuit protects the internal circuits of a semiconductor. The electrostatic discharge protection circuit includes a first electrostatic protection unit connected to a power source supply pad. The first electrostatic protection unit discharges an ESD current into the power source supply pad when an ESD is introduced into the input/output pad, and generates a first driving voltage by utilizing the ESD current flow through a voltage-drop unit. A driver driven by the first driving voltage generates a second driving voltage by an ESD current. A second electrostatic protection unit discharges the introduced ESD current into the power source supply pad by the second driving voltage such that a voltage applied to a gate of the first NMOS transistor is reduced.