ESD Protection Circuit with Current Mirror Capacitance Amplification
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Solution Overview
Problem
Conventional ESD protection circuits in integrated circuits are prone to electrical overstress (EOS) failure during latch-up tests due to excessive current flow through the clamp FET, which is not adequately addressed by existing designs that use a current mirror to reduce capacitor area.
Innovation Solution
The proposed ESD protection circuit includes a current mirror with a specific configuration of transistors and diodes that allows for the amplification of capacitance, enabling the clamp FET to be turned off during latch-up tests, thereby preventing substantial current flow between the source and drain of the clamp FET.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a current mirror is used to reduce capacitor area in ESD protection circuits, then the area of the capacitor is reduced, but the circuit becomes prone to electrical overstress (EOS) failure during latch-up tests due to excessive current flow through the clamp FET
Solution Approach 1:
The circuit is segmented into distinct functional blocks: the ESD protection circuit with clamp FET and capacitor, the latch-up protection circuit with its own transistor and capacitor, and the current mirror. This segmentation allows each block to independently handle specific protection functions, preventing interference between ESD protection and latch-up testing operations.
Solution Approach 2:
The latch-up protection circuit acts as an intermediary between the test equipment and the ESD protection circuit. During latch-up tests, this intermediary circuit detects the test conditions and activates to prevent excessive current from reaching the clamp FET, thereby protecting it from EOS failure while allowing normal ESD protection functionality to remain intact.
2Reliability
If the clamp FET is designed to provide effective ESD discharge, then ESD protection is improved, but the clamp FET is vulnerable to excessive current during latch-up tests causing EOS failure
Solution Approach 1:
The latch-up protection circuit dynamically responds to test conditions by detecting voltage changes across the clamp FET. When excessive current conditions are detected during latch-up tests, the circuit automatically activates to limit the current, whereas during normal ESD events, the circuit remains inactive and allows full ESD protection functionality.
Solution Approach 2:
The latch-up protection circuit is designed to preemptively counteract harmful effects before they can damage the clamp FET. By monitoring conditions and activating before excessive current can cause EOS failure, the circuit prevents damage rather than reacting after failure occurs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively eliminates EOS failures during latch-up tests by ensuring the clamp FET remains off, thus preventing electrical overstress and ensuring the integrated circuit's protection from ESD pulses.
Implementation Method 1
the proposed ESD protection circuit includes a current mirror with a specific configuration of transistors and diodes that allows for the amplification of capacitance
Data Source
AI summary
An electrostatic discharge (ESD) protection circuit includes a clamp transistor, and inverter, a resistance-capacitance (RC) circuit, and a current mirror. The clamp transistor is coupled between a first supply node and a second supply node. The inverter has an input end and an output end, and the output end of the inverter is coupled with a gate of the clamp transistor. The RC circuit is coupled to the first supply node. The current mirror includes a first transistor and a second transistor. The first transistor is coupled between the input end of the inverter and the second supply node, and the second transistor is coupled between the RC circuit and the second supply node.