ESD Protection Circuit with Deep Trench Trigger Diodes
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Solution Overview
Problem
Existing ESD protection circuits face insufficient protection due to high breakdown voltage requirements, which can lead to false triggering and inadequate protection against ESD events, especially when relying on the breakdown of the p/n-well junction, necessitating additional masking and increased manufacturing costs.
Innovation Solution
The integration of a first diode and a resistor in a first region of a semiconductor structure, along with a second diode in a deep trench isolated region, connected in series to provide a controlled trigger voltage for the ESD protection circuit, allowing for tailored trigger voltage settings without the need for a P-doped barrier layer mask, using deep N wells alongside deep trenches to set the breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the breakdown voltage of p/n-well junction is increased to prevent false triggering, then false triggering is reduced, but ESD protection capability deteriorates due to insufficient protection against ESD events
Solution Approach 1:
The patent segments the ESD protection circuit into multiple functional regions: a first region containing a protection transistor with its own p/n-well junction for basic protection, and a second region containing an isolated trigger diode with adjustable breakdown voltage for controlled triggering. This segmentation allows each region to be optimized independently, resolving the contradiction between preventing false triggering and maintaining ESD protection capability.
Solution Approach 2:
The patent introduces a deep trench isolation structure as an intermediary element between the first and second regions. This deep trench filled with dielectric material acts as a physical and electrical barrier, allowing the trigger diode in the second region to be electrically isolated from the protection transistor in the first region while still being part of the same integrated circuit structure. This enables independent voltage breakdown control without interference.
2Reliability
If a P-doped barrier layer mask is used to achieve high breakdown voltage, then breakdown voltage is increased, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the trigger diode function into a separate second region that is electrically isolated from the main protection transistor structure. By taking out the trigger diode and placing it in an isolated region defined by deep trenches, the design eliminates the need for complex P-doped barrier layer masking processes while achieving the desired high breakdown voltage through the isolated diode's controlled junction depth and doping profile.
Solution Approach 2:
The patent changes the key parameter from relying on P-doped barrier layer masking to controlling the breakdown voltage through the isolated trigger diode's physical structure (junction depth, doping concentration, and area). This parameter change allows high breakdown voltage to be achieved through geometric and doping control rather than complex masking processes, reducing manufacturing complexity.
3Reliability
If the trigger voltage is set above the maximum signal level with margin, then false triggering is prevented, but protection against ESD events becomes insufficient
Solution Approach 1:
The patent creates a dynamic triggering mechanism where the isolated trigger diode's breakdown voltage can be precisely controlled to match the desired protection threshold. Unlike fixed breakdown voltages in conventional designs, the isolated diode's breakdown characteristics can be dynamically adjusted through doping profiles and geometric parameters, allowing the trigger voltage to be set optimally for both signal operation stability and ESD protection adequacy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively enhances ESD protection by ensuring proper triggering of the protection transistor at lower voltages, preventing false triggering and maintaining circuit integrity during ESD events without the need for additional masking, thus reducing manufacturing costs and improving protection against excessive positive or negative ESD voltages.
Implementation Method 1
The trigger voltage of certain ESD protection clamps are triggered by voltage breakdown of a p/n-well junction. However, this breakdown level may be significantly higher than the normal signal level for a protected node
Implementation Method 2
lateral NPN bipolar transistors can be triggered by carrier injection into the base to conduct ESD event current to protect an I/O pad
Implementation Method 3
a second diode formed in a second region isolated from the first region by a deep trench
Data Source
AI summary
Disclosed examples include integrated circuits, fabrication methods and ESD protection circuits to selectively conduct current between a protected node and a reference node during an ESD event, including a protection transistor, a first diode and a resistor formed in a first region of a semiconductor structure, and a second diode formed in a second region isolated from the first region by a polysilicon filled deep trench, where the first and second diodes include cathodes formed by deep N wells alongside the deep trench in the respective first and second regions to use integrated deep trench diode rings to set the ESD protection trigger voltage and prevent a parasitic deep N well/P buried layer junction from breakdown at lower than the rated voltage of the host circuitry.