ESD Protection Device Double Well Structure Parasitic Resistance
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Solution Overview
Problem
Large ESD protection circuits in semiconductor devices hinder the trend of increased circuit integration and decreased chip size due to their size and parasitic resistance, which can lead to heat generation and damage from electrostatic discharges.
Innovation Solution
The design of an ESD protection device with a double well structure in the substrate, featuring heavily doped regions of opposite conductivity types without a device isolation structure between them, allowing for a shorter current path and reduced parasitic resistance, thereby enhancing ESD protection while enabling scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the ESD protection circuit is increased to improve ESD protection characteristics, then the ESD protection capability is improved, but the chip size increases and circuit integration is hindered
Solution Approach 1:
The patent transitions from a planar ESD protection structure to a three-dimensional vertical structure by forming a deep well extending into the substrate. This vertical dimension allows the ESD protection circuit to achieve better discharge characteristics without increasing the horizontal chip area, effectively resolving the contradiction between ESD protection capability and chip size.
Solution Approach 2:
The patent implements a nested structure where an inner well is formed within the outer well, creating a multi-layered configuration. This nesting approach maximizes the ESD protection functionality within a compact volume, providing enhanced protection characteristics while maintaining small chip footprint.
2Reliability
If the size of the ESD protection circuit is increased to reduce parasitic resistance, then the parasitic resistance is reduced, but heat generation increases due to larger device area
Solution Approach 1:
The patent applies local quality by creating heavily doped regions specifically at critical locations within the well structure. These localized high-doping areas reduce parasitic resistance where it matters most for ESD discharge, while the overall device area remains compact, thereby minimizing heat generation.
Solution Approach 2:
The patent introduces an intermediate structure (the deep well with inner and outer wells) that acts as a mediator between the ESD discharge path and the substrate. This intermediate structure provides a controlled path for charge dissipation, reducing parasitic resistance without requiring large device area that would generate excessive heat.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively protects semiconductor devices from electrostatic discharges by minimizing heat generation and parasitic resistance, allowing for smaller, more integrated ESD protection devices.
Implementation Method 1
Electrostatic discharge (ESD) can result from a variety of factors, such as exposure to an electrostatic field or direct contact with an item carrying electrostatic charge. ESD can be particularly damaging to electronic devices, such as semiconductor devices.
Implementation Method 2
Large ESD protection circuits run counter to the industry trend of increased circuit integration and decreased chip size. However, large ESD protection circuits run counter to the industry trend of increased circuit integration and decreased chip size.
Data Source
AI summary
An electrostatic discharge (ESD) device includes a substrate, an external well of a first conductivity type in the substrate, and an internal well of a second conductivity type in the external well, the first conductivity type opposite the second conductivity type. The ESD device further includes a first heavily doped region of the first conductivity type located at a surface of the internal well, a second heavily doped region of the second conductivity type located at a surface of the internal well, and a third heavily doped region of the first conductivity type located at a surface of the external well. The second heavily doped region is interposed between and spaced from each of the first and third heavily doped regions, and at least one of a space between the first and second heavily doped regions and a space between the second and third heavily doped regions is devoid of a device isolation structure of electrical isolation material.