ESD Protection Circuit Using Driving Transistor to Reduce Clamping Voltage
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Solution Overview
Problem
In advanced semiconductor technologies like 130 nm SiGe BiCMOS, the clamping voltage of traditional ESD protection circuits using stacked diodes is too high due to low collector-emitter breakdown voltage and oxide breakdown voltage, which is detrimental for integrated electronic circuits.
Innovation Solution
An ESD protection circuit utilizing a series of bipolar junction transistors with a driving circuit to supply base current to ESD current conducting transistors during an ESD event, reducing the clamping voltage while maintaining low parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If multiple bipolar transistors are stacked in series to reduce parasitic capacitance, then parasitic capacitance is reduced, but clamping voltage increases to N times Vbe(on)
Solution Approach 1:
The ESD current path is segmented into multiple transistor stages, where each stage handles a portion of the ESD current. The first transistor Q1 conducts the full ESD current, while subsequent transistors Q2-QN conduct progressively smaller base currents, allowing the chain to achieve low capacitance without requiring all transistors to sustain full ESD current through their collector-emitter paths
Solution Approach 2:
The invention changes the current conduction parameters of each transistor in the chain. Instead of all transistors conducting full ESD current (which would require high breakdown voltage), the transistors are configured to conduct decreasing currents from Q1 to QN, with Q1 handling the full ESD current and downstream transistors handling only base currents, thereby reducing the required collector-emitter breakdown voltage of each transistor
2Shape
If the number of bipolar transistors in series is increased to reduce capacitance, then parasitic capacitance decreases, but the required collector-emitter breakdown voltage increases
Solution Approach 1:
The ESD current path is segmented into multiple transistor stages, where each stage handles a portion of the ESD current. The first transistor Q1 conducts the full ESD current, while subsequent transistors Q2-QN conduct progressively smaller base currents, allowing the chain to achieve low capacitance without requiring all transistors to sustain full ESD current through their collector-emitter paths
Solution Approach 2:
The invention changes the current conduction parameters of each transistor in the chain. Instead of all transistors conducting full ESD current (which would require high breakdown voltage), the transistors are configured to conduct decreasing currents from Q1 to QN, with Q1 handling the full ESD current and downstream transistors handling only base currents, thereby reducing the required collector-emitter breakdown voltage of each transistor
3Shape
If traditional stacked diode configuration is used, then low parasitic capacitance is achieved, but clamping voltage becomes too high for advanced technologies
Solution Approach 1:
The invention changes the current conduction parameters of each transistor in the chain. Instead of all transistors conducting full ESD current (which would require high breakdown voltage), the transistors are configured to conduct decreasing currents from Q1 to QN, with Q1 handling the full ESD current and downstream transistors handling only base currents, thereby reducing the required collector-emitter breakdown voltage of each transistor
Solution Approach 2:
The invention introduces dynamic current distribution across the transistor chain during ESD events. The first transistor Q1 dynamically conducts the full ESD current surge, while downstream transistors Q2-QN dynamically conduct only the base currents required to maintain Q1's conduction, allowing the system to adapt to ESD stress conditions without requiring all components to be rated for full ESD current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a lower clamping voltage with reduced parasitic capacitance, enhancing ESD protection and leakage current characteristics, particularly beneficial for RF devices and power clamps.
Implementation Method 1
the base-emitter voltage of each driving transistor is much smaller than the base-emitter voltage of an ESD current conducting transistor which conducts the full ESD current IESD. Since the base-emitter current paths of the driving transistor(s) are in parallel over one or more of the ESD current conducting transistor(s), the total voltage over the terminals can be significantly reduced.
Data Source
AI summary
Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q1, Q2, Q4) in a main ESD current conducting path between a first and a second terminal (T1, T2), and further comprises at least one driving transistor (Q3) connected in parallel to at least one of the ESD current conducting transistors (Q1) and provided for conducting a driving current (Ib2) to one or more of the ESD current conducting transistors (Q3) on occurrence of an ESD event.