Off-Chip ESD Protection via Edge Wrap and TSV Connectors
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Solution Overview
Problem
Existing semiconductor device manufacturing techniques for electrostatic discharge (ESD) protection, such as wire bonding, face limitations in high-frequency operations due to inductance and impedance issues, which can lead to excessive ESD stress on IC chips, especially as technology advances to smaller feature sizes and faster speeds.
Innovation Solution
The use of edge wrap and through-silicon via (TSV) connectors to create a robust ESD protection structure by stacking an unprotected IC chip on an ESD protection chip, allowing for lower inductance and impedance electrical connections, thereby enabling faster I/O operating speeds and reducing the hazard of ESD damage during handling and packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to connect ESD protection circuit to IC chip, then the ESD protection circuit can be placed off-chip, but the inductance of wire bonds limits high-frequency performance and increases impedance
Solution Approach 1:
The ESD protection circuit is extracted from the IC chip and placed on a separate substrate, allowing the chip layout to be optimized for high-speed performance while the ESD protection function is provided externally. This extraction enables the use of lower-inductance connection methods such as TSVs and edge wrap connectors instead of traditional wire bonds.
Solution Approach 2:
An intermediate substrate is introduced that contains TSVs and edge wrap connectors to mediate the connection between the IC chip and the ESD protection circuit. This intermediary structure provides low-inductance, low-impedance electrical paths that overcome the limitations of direct wire bonding while enabling effective ESD protection.
2Speed
If wire bonds are used in parallel with I/O connections, then high-speed operation is maintained, but the series inductance prevents quick ESD response and allows excessive stress voltage
Solution Approach 1:
The intermediate substrate with TSVs and edge wrap connectors acts as a mediator that provides a low-inductance path for ESD current. This intermediary structure enables the ESD protection circuit to respond quickly to ESD events while maintaining the high-speed performance of the I/O connections, resolving the conflict between speed and protection effectiveness.
3Area of moving object
If smaller semiconductor feature sizes are used to improve IC technology, then integration density increases, but ESD stress voltage becomes excessive due to lower inductance requirements
Solution Approach 1:
By extracting the ESD protection circuit from the chip and placing it on a separate substrate with specialized low-inductance connections, the chip area can be fully utilized for high-density circuit implementation. The external ESD protection structure provides the necessary current handling capability without constraining the chip's feature size reduction and area optimization.
Solution Approach 2:
The ESD protection structure uses composite construction combining TSVs, edge wrap connectors, and substrate materials to achieve extremely low inductance and impedance. This composite approach provides the robust ESD protection needed for small-feature-size chips while maintaining the benefits of high integration density.
Data Source
AI summary
A method and apparatus for off-chip ESD protection, the apparatus includes an unprotected IC 22 stacked on an ESD protection chip 24 and employing combinations of edge wrap 32 and through-silicon via connectors 44 for electrical connection from an external connection lead 34 on a chip carrier 84 or system substrate 64, to an ESD protection circuit, and to an I/O trace 46 of the unprotected IC 22. In one embodiment the invention provides an ESD-protected stack 50 of unprotected IC chips 52, 54 that has reduced hazard of mechanical and ESD-damage in subsequent handling for assembly and packaging. The method includes a manufacturing method 170 for mass producing embedded edge wrap connectors 32, 38 during the chip manufacturing process.