ESD Protection Fin Structure for Semiconductor Integrated Circuit
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Solution Overview
Problem
Existing semiconductor integrated circuit devices using fin field effect transistors (FETs) or nanowire FETs face challenges in effectively protecting internal circuits from electrostatic discharge (ESD) due to limitations in current flow during ESD events, which can cause damage.
Innovation Solution
The integration of an ESD protection circuit with specific fin or pad structures and interconnect configurations, where the second conductivity type structures have a greater width and are opposed to the first conductivity type structures, allowing for swift current flow to diodes during ESD events, thereby reducing damage to internal circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits are used, then basic protection is provided, but large current cannot flow swiftly during ESD events causing damage to internal circuits
Solution Approach 1:
The patent applies asymmetry by making the second fin structure (connected to signal interconnect) wider than the first fin structure (connected to power interconnect). This asymmetric design allows the signal path to have lower resistance and enable faster current flow during ESD events, directly resolving the contradiction between protection effectiveness and current flow speed.
Solution Approach 2:
The patent implements local quality by creating different fin structure characteristics in different regions: the first fin structure has standard dimensions for power supply stability, while the second fin structure has increased width for optimized current flow. This localized differentiation allows each region to be optimized for its specific function, improving both reliability and current flow speed.
2Reliability
If fin structure width is increased to allow larger current flow, then ESD protection is improved, but device area increases
Solution Approach 1:
The asymmetric fin structure design allows selective widening only where needed (second fin structure for signal path) rather than uniformly increasing all fin dimensions. This targeted approach improves ESD protection capability through enhanced current flow in critical paths while minimizing the overall device area increase.
Solution Approach 2:
The patent utilizes the vertical dimension by employing multiple interconnect layers (first and second interconnect layers) to route power and signal connections. This multi-layer approach allows current to flow through three-dimensional paths, effectively increasing protection capability without proportionally increasing the planar device footprint.
Data Source
AI summary
An ESD protection circuit includes a first fin structure having fins of a first conductivity type and a second fin structure having fins of a second conductivity type, the second fin structure being opposed to the first fin structure. A first power interconnect connected with the first fin structure and a signal interconnect connected with the second fin structure are formed in a first interconnect layer, and a second power interconnect connected with the first power interconnect is formed in a second interconnect layer. The width occupied by the second fin structure is greater than that of the first fin structure, and the width of the signal interconnect is greater than that of the first power interconnect.