ESD Protection Circuit Using Floating Base Transistors
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Solution Overview
Problem
Conventional electrostatic discharge (ESD) protection circuits in semiconductor ICs clamp input signals within a limited voltage range, restricting the operating swing and failing to protect against high electrostatic voltages while allowing non-electrostatic voltage signals to be faithfully conveyed.
Innovation Solution
A circuit comprising three transistors with floating bases or bodies, connected in parallel between a signal line and a fixed voltage level, allowing greater input voltage swings without clamping, using parasitic BJTs and a MOS field transistor to remain cut off within specific voltage ranges and conduct during electrostatic events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits with back-to-back diodes are used, then protection against electrostatic discharge is provided, but input signal clamping occurs and operating voltage swing is restricted
Solution Approach 1:
The patent changes the operating parameters of the protection circuit by using transistors with floating bases/bodies that remain in cutoff mode during normal operation. This allows the circuit to tolerate voltage swings beyond traditional diode clamp levels without conducting, thereby expanding the usable voltage range while maintaining ESD protection capability when actual electrostatic events occur.
2Reliability
If diodes are used to clamp positive and negative voltage transitions, then gate oxide protection is achieved, but signal fidelity is lost for voltages outside the clamped range
Solution Approach 1:
The patent implements preliminary protection by designing a circuit that preemptively withstands voltage excursions without reacting. The floating base/bbody configuration creates a preliminary defense mechanism that remains inactive during normal signal variations, allowing full signal fidelity, while automatically activating only when genuine ESD threats exceed the expanded tolerance threshold.
3Reliability
If protection circuits are placed between input pads and transistor gates, then ESD damage is prevented, but the circuits cannot handle input voltages higher than Vcc or lower than Vss
Solution Approach 1:
The patent introduces dynamic characteristics to the protection circuit through transistors that can transition between cutoff and conducting states based on the nature of the input voltage. During normal operation, the transistors remain in cutoff mode, dynamically adapting to voltage swings beyond traditional limits. When ESD events occur, the transistors dynamically switch to conducting mode to provide protection, thus achieving both extended adaptability and reliable protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables protection against electrostatic discharges while maintaining the full range of input voltage swings, preventing signal clamping and ensuring reliable operation across a broader voltage range.
Implementation Method 1
The parasitic BJTs and the MOS field transistor are configured to remain in a cutoff mode so long as an input voltage at the pad is between a negative V1 (−V1) voltage (V1>0) and a +V2 voltage (V2>Vcc)
Implementation Method 2
If the voltage applied to the gate insulator becomes excessive, the gate oxide can break down... the dielectric breakdown strength of silicon dioxide... is approximately 8×106 V/cm
Data Source
AI summary
An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs) each with a floating base and a metal oxide semiconductor (MOS) field transistor with a floating body is disclosed. The three transistors may be connected in parallel between a bond (input or output) pad and a substantially fixed voltage level (e.g., a ground (or zero potential) or Vcc, depending on the transistor configuration) in a semiconductor electronic device so as to protect transistor gates or other circuit portions from damage from electrostatic voltages. The parasitic BJTs and the field transistor may be configured to remain cut off so long as an input voltage at the pad is between a negative V1 voltage (−V1) (V1>0) and a +V2 voltage (V2>Vcc), thereby allowing a greater input voltage swing without signal clamping.