Electrostatic Protection Circuit Gate Voltage Control
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Solution Overview
Problem
Existing electrostatic protection circuits face challenges in maintaining gate voltage within permissible limits during normal operation while ensuring high discharge performance during electrostatic discharge (ESD) surges, as they often fail to suppress voltage rises caused by successive pulse signals.
Innovation Solution
The proposed electrostatic protection circuit design includes two transistors connected in series, with specific gate control mechanisms to manage voltage levels, using a buffer circuit and additional transistors to prevent excessive voltage on the high potential side transistor during both ESD and pulse signal inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a first MOS transistor is connected between an input line and an internal node with its gate electrode connected to a power source line, then the transistor provides a simple protection structure, but the gate voltage rises excessively during successive pulse signals causing the transistor to enter normally ON state and lose protection capability
Solution Approach 1:
A second MOS transistor is introduced as an intermediary device between the power source line and the gate electrode of the first MOS transistor. This second transistor acts as a controlled switch that regulates the voltage supplied to the gate, preventing excessive voltage rises during successive pulse signals while maintaining simple overall circuit structure.
Solution Approach 2:
The invention dynamically changes the gate voltage parameter of the first MOS transistor by controlling the second MOS transistor. During normal operation, the second transistor maintains the first transistor in protection mode. During ESD events, the second transistor switches states to allow the first transistor to enter normally ON state for high discharge performance, thus adapting the protection level according to operating conditions.
2Reliability
If the first MOS transistor is maintained in normally OFF state during normal operation, then protection capability is maintained, but ESD discharge performance is reduced; if allowed to enter normally ON state, then ESD discharge performance improves, but gate voltage control is lost during pulse signals
Solution Approach 1:
The invention makes the operating state of the first MOS transistor dynamic rather than static. The second MOS transistor serves as a dynamic controller that adjusts the gate voltage of the first transistor based on the type of signal detected. During successive pulse signals, it maintains control to prevent normally ON state. During ESD surges, it allows the first transistor to switch to normally ON state for optimal discharge performance.
Solution Approach 2:
The gate control circuit monitors the voltage conditions at the gate electrode of the first MOS transistor and provides feedback control through the second MOS transistor. This feedback mechanism ensures that during successive pulse signals, the gate voltage is kept within safe limits, while during ESD events, the feedback allows controlled transition to normally ON state for enhanced discharge capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses gate voltage rises during pulse signals and enhances ESD discharge performance by maintaining a stable voltage level, preventing damage and ensuring the circuit operates within safe voltage limits.
Implementation Method 1
a third transistor that is connected between a power source line and a gate of the first transistor; and a fourth transistor that is connected between the power source line and the gate of the first transistor in a direction opposite to a direction of the third transistor
Implementation Method 2
electrostatic protection circuits that protect semiconductor devices from electrostatic discharge (ESD)
Data Source
AI summary
An electrostatic protection circuit includes a first transistor connected to an external terminal, a second transistor that is connected in series to the first transistor and that is in a normally OFF state. The electrostatic protection circuit includes a third transistor that is connected between a power source line and a gate of the first transistor, and a fourth transistor that is connected between the power source line and the gate of the first transistor in the opposite direction to the third transistor.