ESD Protection Device With Guard Ring and Local Doping
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Solution Overview
Problem
Advanced CMOS IC devices are susceptible to electrostatic discharge (ESD) damage due to their miniaturization, leading to latchup issues caused by smaller holding voltages in current ESD protection devices.
Innovation Solution
A semiconductor device design incorporating a doped well, drain region, source region, and guard ring with a complementary conductive type doped region adjacent to the parasitic NPN BJT, increasing the doped concentration of the base and thus the holding voltage for enhanced ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current ESD protection devices are used in miniaturized CMOS IC devices, then ESD protection is provided, but the holding voltage is smaller making the device susceptible to latchup issues
Solution Approach 1:
The patent introduces a first doped region with first conductive type adjacent to the emitter of the parasitic NPN BJT, creating a localized doped region with complementary conductive type. This local modification increases the doped concentration of the base of the parasitic NPN BJT specifically where needed, thereby increasing the holding voltage and reducing latchup susceptibility without affecting the overall ESD protection function
Solution Approach 2:
The patent changes the doping concentration parameter by introducing an additional doped region with higher doped concentration adjacent to the emitter. This parameter change directly increases the holding voltage of the parasitic NPN BJT, addressing the latchup issue while maintaining the ESD protection capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly improves ESD tolerance and holding voltage, preventing damage to main circuits by allowing ESD current to safely discharge through the parasitic NPN BJT to a low voltage site.
Implementation Method 1
The first doped region is disposed in the doped well between the drain region and the source region, wherein the first doped region has the first conductive type and is in contact with the doped well and the source region
Data Source
AI summary
A semiconductor device for electrostatic discharge (ESD) protection includes a doped well, a drain region, a source region, a first doped region and a guard ring. The doped well is disposed in a substrate and has a first conductive type. The drain region is disposed in the doped well and has a second conductive type. The source region is disposed in the doped well and has the second conductive type, wherein the source region is separated from the drain region. The doped region is disposed in the doped well between the drain region and the source region, wherein the doped region has the first conductive type and is in contact with the doped well and the source region. The guard ring is disposed in the doped well and has the first conductive type.