ESD Protection Device Holding Voltage via Segmented Doped Regions
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Solution Overview
Problem
Current semiconductor devices for electrostatic discharge (ESD) protection have a lower holding voltage compared to external elements, leading to latchup issues, and increasing the trigger voltage is not feasible without compromising device performance.
Innovation Solution
A semiconductor device design incorporating a first doped well, gate, drain region, second doped well, first doped region, second doped region, and source region, where a dummy P+ doped region or P+ doped region is electrically connected to the source region, forming additional current paths with increased resistance to enhance holding voltage without raising the trigger voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current ESD protection device design is used, then the device structure is simple, but the holding voltage is lower than external elements causing latchup issues
Solution Approach 1:
The ESD protection device is segmented into multiple functional regions including a first doped well with drain region, a second doped well with first and second doped regions, and a source region. This segmentation allows each region to contribute differently to the overall holding voltage, enabling the device to achieve higher holding voltage without proportionally increasing overall complexity.
Solution Approach 2:
Different doped regions are strategically positioned within the device structure with specific doping types and concentrations. The first doped region has second conductivity type while the second doped region has first conductivity type, creating localized electrical properties that collectively enhance the holding voltage without requiring uniform complexity throughout the entire device.
2Reliability
If series-connected elements are used to increase holding voltage, then the holding voltage increases, but the device size increases
Solution Approach 1:
Multiple doped regions (first doped region and second doped region with complementary conductivity types) are merged into a single integrated device structure rather than using separate series-connected elements. This merging achieves the cumulative holding voltage effect of multiple elements while maintaining a compact footprint, thereby increasing holding voltage without proportionally increasing device area.
Solution Approach 2:
The device structure employs a nested arrangement where the first doped well and second doped well are disposed within the substrate at opposite sides of the gate, with doped regions nested within their respective wells. This nested configuration maximizes the use of vertical and lateral space, enabling complex functionality in a minimized device footprint.
Data Source
AI summary
A semiconductor device for ESD protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is disposed in a substrate at a first side of a gate and the drain region has a first conductivity type. The first doped region is disposed in a second doped well at a second side of the gate and has a second conductivity type. The source region is also disposed in the second doped well and has the first conductive type, and the source region surrounds the first doped region from a topview. The second doped region is disposed in the second doped well and has the second conductive type, and the second doped region is disposed between the gate and the source region, wherein a plurality of contacts is electrically connected to the second doped region.