ESD Protection Circuit Using Intrinsic Power-Ground Capacitance
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Solution Overview
Problem
Conventional ESD protection circuits require large layout areas due to the use of big capacitors and resistors to differentiate between ESD events and regular operations, leading to increased chip density and design costs.
Innovation Solution
The proposed protection circuit utilizes intrinsic capacitors between power and ground pads to create an RC network for ESD protection, eliminating the need for additional capacitors and reducing layout area by using a trigger circuit, reverse-trigger circuit, and ESD clamp circuit to manage voltage differences and prevent ESD current interference during regular operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits use big capacitors and resistors to form RC network for differentiating ESD events and regular operations, then the ESD protection reliability is improved, but the layout area increases significantly
Solution Approach 1:
The patent utilizes the intrinsic capacitor that already exists between the power pad and ground pad in the chip structure. This intrinsic capacitor serves dual purposes: it is both part of the normal power supply structure and functions as the timing capacitor for ESD detection, eliminating the need for separate dedicated capacitors and significantly reducing layout area while maintaining ESD protection reliability
Solution Approach 2:
The intrinsic capacitor between power pad and ground pad is made to serve multiple functions: it acts as both the power supply decoupling capacitor and the ESD detection timing capacitor. This multi-functionality approach allows the same physical structure to fulfill both normal operation and ESD protection requirements, resolving the contradiction between reliability and area
2Measurement precision
If conventional ESD protection circuits use large value capacitors and resistors, then the ESD event differentiation capability is improved, but the chip density decreases and design costs increase
Solution Approach 1:
The intrinsic capacitor inherent in the power pad to ground pad structure is utilized as the timing element for ESD detection. This eliminates the need for separate large-value capacitors that would reduce chip density, while the RC time constant formed with the intrinsic resistance maintains the ability to differentiate ESD events from regular operations
Solution Approach 2:
The patent changes the parameter approach by using the naturally occurring intrinsic capacitance value rather than requiring externally added large capacitors. The RC time constant is achieved through the combination of this intrinsic capacitance with circuit resistance, maintaining the necessary time constant for ESD detection while improving chip density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the layout area required for ESD protection, enhancing chip density and reducing design costs while maintaining effective ESD current bypassing capabilities.
Implementation Method 1
the conventional ESD protection circuit connects a resistor and a capacitor in series to the pad to form a RC network for differentiating different rising times of the voltage of the pad
Implementation Method 2
when an ESD event happens, such as human bodies or manufacturing machines accidentally contacting the pad of a chip, the massive electrostatic currents of the ESD power source flow through the pad into the chip
Data Source
AI summary
An electro-static discharge, ESD, protection circuit is disclosed. While protecting an ESD event between a given pad and a ground pad, the ESD protection circuit triggers a clamp for ESD protection according to a voltage difference between the given pad and a power pad. Generally, chips already have capacitance between the power pads and the ground pads, such as capacitance contributed by decoupling capacitors for power regulation. Therefore, when the ESD event happens between the given pad and the ground pad, voltage of the power pad holds to make a voltage difference enough for triggering the clamp. Accordingly, the ESD protection circuit can reduce layout area by taking advantage of the original capacitance of chips.