ESD Protection Circuit Using LDD CMOS Triggering Diode

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Solution Overview

Problem

Current high voltage electrostatic discharge (ESD) protection circuits require additional masks and occupy larger areas, making them expensive and inefficient for manufacturing.

Innovation Solution

A compact ESD protection circuit configuration using lightly doped drain (LDD) CMOS technologies with P-substrate and PMOS/NMOS devices, incorporating a triggering diode and transient voltage suppressing (TVS) circuit with specific dopant profiles and silicon controlled rectifier (SCR) to achieve high breakdown voltages without additional masks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional masks are used in manufacturing high voltage ESD protection circuits, then the breakdown voltage and protection performance are improved, but the manufacturing cost and process complexity increase

Engineering Contradiction:

Improvebreakdown voltageVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the ESD protection function with standard LDD CMOS device structures by integrating the triggering diode and TVS circuit into the existing PMOS/NMOS device architecture. The P-drain dopant profile of the PMOS transistor is utilized to form the triggering diode anode, eliminating the need for separate masking steps that would otherwise be required to create these protective structures.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The PMOS transistor structure serves multiple functions: it acts as both the main protective element and provides the triggering mechanism through its P-drain region. The same dopant implantation process that creates the PMOS device also creates the triggering diode, making the structure universal and eliminating additional manufacturing steps.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If additional masks are used in manufacturing high voltage ESD protection circuits, then the protection performance is improved, but the device complexity and manufacturing steps increase

Engineering Contradiction:

Improveprotection performanceVSAvoidmanufacturing steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple protective functions into the standard LDD CMOS fabrication process. The triggering diode is formed by utilizing the existing P-drain region of the PMOS transistor, and the TVS circuit is integrated using the same dopant profiles, thereby merging ESD protection manufacturing with standard device fabrication without adding complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The PMOS transistor's own P-drain region serves as the triggering mechanism for the ESD protection circuit. The dopant profile already present in the PMOS device self-provides the necessary structure for the triggering diode, eliminating the need for external or additional structures that would require separate manufacturing steps.

Inventive Principle:

Principle #25Self-service

3Reliability

If high voltage ESD protection circuits are designed with traditional configurations, then the breakdown voltage is achieved, but the device area occupancy increases

Engineering Contradiction:

Improvebreakdown voltageVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the ESD protection circuit with the standard CMOS device layout by utilizing the existing PMOS and NMOS transistor structures. The triggering diode is formed within the PMOS device footprint, and the TVS circuit shares the same physical space, thereby achieving high voltage protection without increasing the overall device area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The triggering diode is nested within the PMOS transistor structure, with the diode anode formed by the P-drain region that is already part of the PMOS device. The TVS circuit is similarly nested, utilizing the same dopant profiles and physical space, thereby achieving compact integration of multiple protective functions.

Inventive Principle:

Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables effective high voltage ESD protection with reduced area occupancy and manufacturing costs, achieving breakdown voltages up to 22 volts for PMOS and 25 volts for NMOS devices, while maintaining a compact device configuration.

Implementation Method 1

the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied

Methodology Applied

Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS8937356B2Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies

Publication Date: 2015.01.20 ALPHA & OMEGA SEMICONDUCTOR INC

AI summary

An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration.