ESD Protection Circuit with Low Parasitic Capacitance
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Solution Overview
Problem
Conventional ESD protection circuits exhibit high parasitic capacitance, which can lead to damage in integrated circuits due to electrostatic discharge, necessitating a solution that reduces junction capacitance while maintaining protection efficiency.
Innovation Solution
An ESD protection circuit with low parasitic capacitance is designed, utilizing a first bipolar junction transistor and an ESD power clamp device connected between an I/O terminal and ground, with alternative configurations including Zener diodes, PNP or NPN transistors, and diode elements to form effective ESD protection paths for both positive and negative pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional steering diode scheme is used for ESD protection, then ESD protection function is provided, but parasitic capacitance becomes extremely high
Solution Approach 1:
The patent segments the ESD protection function into two separate circuits: a first ESD protection circuit for positive ESD events and a second ESD protection circuit for negative ESD events. Each circuit uses a unipolar structure (either NPN or PNP transistor) instead of the conventional bipolar steering diode configuration. This segmentation allows each circuit to be optimized for its specific polarity, reducing the overall parasitic capacitance while maintaining comprehensive ESD protection functionality.
2Reliability
If bipolar steering diode configuration is used, then ESD protection is achieved, but junction capacitance increases resulting in exorbitant outcome
Solution Approach 1:
The patent applies local quality by making each ESD protection circuit unipolar in nature - the first circuit uses only NPN transistors for positive ESD protection, while the second circuit uses only PNP transistors for negative ESD protection. This local optimization of transistor polarity reduces the junction capacitance in each circuit compared to the conventional bipolar configuration, while the combination of both circuits provides comprehensive bidirectional ESD protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces parasitic capacitance, providing reliable ESD protection with reduced junction capacitance, thus enhancing the reliability and lifetime of integrated circuits.
Implementation Method 1
Electrostatic discharge (ESD) is a phenomenon that releases and transfers charges between integrated circuit chips and external objects
Implementation Method 2
the junction capacitance of such prior scheme will be equal to the capacitance of the first diode D1 and the second diode D2, i.e. (D1+D2), resulting in an extremely high capacitance
Data Source
AI summary
An Electrostatic Discharge protection circuit with low parasitic capacitance is provided, comprising a first bipolar junction transistor and a first ESD power clamp device. The first bipolar junction transistor is an NPN type of bipolar junction transistor, including a base and an emitter commonly connected to an I/O terminal and a collector connected with the first ESD power clamp device. The first ESD power clamp device is further connected to ground, and can be a Zener diode, PNP type, NPN type of bipolar junction transistor or the like. When a positive ESD pulse is injected, an ESD protection path is consisting of the first bipolar junction transistor and the first ESD power clamp device. When a negative ESD pulse is injected, the ESD protection path is consisting of a parasitic silicon controlled rectifier, thereby reducing parasitic capacitance effectively.