High Voltage ESD Protection for MEMS Microphones
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Solution Overview
Problem
Existing ESD protection circuitry for high voltage I/O in MEMS microphones, particularly in deep submicron CMOS processes, is inadequate due to the sensitivity of MOS devices and the thin gate oxide, which is prone to damage from electrostatic discharges.
Innovation Solution
Implementing high voltage ESD power rail clamps using stacked standard low voltage transistors with NWELL/DNWELL regions and Laterally Diffused MOS (LDMOS) transistors, which increase the breakdown voltage from 10 V to 45 V in a standard 0.18 CMOS process, allowing ESD protection without the need for an expensive high voltage process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard low voltage CMOS process is used, then manufacturing cost is reduced and ease of manufacture is improved, but breakdown voltage remains low (10 V) and ESD protection capability deteriorates
Solution Approach 1:
The ESD protection circuit is segmented into multiple stacked transistors (first transistor and second transistor in series) to distribute and manage high voltage stress across individual devices. This segmentation allows the use of standard low voltage CMOS transistors while achieving high voltage ESD protection capability, resolving the contradiction between using standard processes and achieving high breakdown voltage.
Solution Approach 2:
The invention changes the electrical parameters of the transistor structure by forming high voltage NWELL/DNWELL regions and using LDMOS transistors to increase the breakdown voltage from 10 V to 45 V in a standard 0.18 CMOS process. This parameter change enables ESD protection without requiring expensive high voltage process modifications.
2Reliability
If high voltage process is used, then breakdown voltage is increased to 45 V and ESD protection capability is improved, but manufacturing cost increases and ease of manufacture deteriorates
Solution Approach 1:
The protection circuit is divided into stacked transistors that can be implemented using standard low voltage CMOS process, avoiding the need for expensive high voltage process modifications while achieving the required 45 V breakdown voltage for ESD protection.
Solution Approach 2:
The invention uses standard low voltage CMOS transistor structures (copying proven, well-manufactured devices) and modifies their electrical characteristics through NWELL/DNWELL region formation and LDMOS implementation to achieve high voltage ESD protection, rather than creating entirely new high voltage device structures.
3Volume of moving object
If thin gate oxide is used, then device size is reduced and integration density is improved, but sensitivity to ESD damage increases and reliability deteriorates
Solution Approach 1:
The invention applies different structural qualities to different parts of the transistor: standard thin gate oxide is used in the channel region for high integration density, while high voltage NWELL/DNWELL regions and LDMOS structures are implemented in the drain and substrate regions to provide ESD protection. This local differentiation resolves the contradiction between thin oxide and ESD robustness.
Solution Approach 2:
The high voltage NWELL/DNWELL regions act as intermediary structures between the thin gate oxide transistor and the substrate, providing a buffer zone that protects the thin oxide from ESD damage while allowing the transistor to maintain its small size and high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides effective ESD protection for MEMS microphones by increasing the breakdown voltage, reducing the need for expensive high voltage processes, and integrating ESD protection into a standard low voltage CMOS process, thereby enhancing the reliability and cost-effectiveness of the microphone interface electronics.
Implementation Method 1
Implementing high voltage ESD power rail clamps using stacked standard low voltage transistors with NWELL/DNWELL regions and Laterally Diffused MOS (LDMOS) transistors, which increase the breakdown voltage from 10 V to 45 V
Data Source
AI summary
An electronics chip includes a charge pump and at least one high voltage (HV) electro-static discharge (ESD) module. The charge pump is configured to provide a predetermined voltage across a microphone. The devices described herein are implemented in a standard low voltage CMOS process and has a circuit topology that provides an inherent ESD protection level (when it is powered down), which is higher than the operational (predetermined) DC level. At least one high voltage (HV) electro-static discharge (ESD) module is coupled to the output of the charge pump. The HV ESD module is configured to provide ESD protection for the charge pump and a microelectromechanical system (MEMS) microphone that is coupled to the chip. The at least one HV ESD module includes a plurality of PMOS or NMOS transistors having at least one high voltage NWELL/DNWELL region formed within selected ones of the PMOS or NMOS transistors. The at least one high voltage NWELL/DNWELL region has a breakdown voltage sufficient to allow a low voltage process to be used to construct the chip and still allow the HV ESD module to provide ESD protection for the chip.