Semiconductor ESD Protection via Multi-Layer Metal Web Structure

The patent transitions from a conventional single-layer metal connection to a multi-layer metal structure with vertical stacking. The first and second metal layers are arranged in different horizontal planes and connected through vertical vias, creating a three-dimensional web structure that distributes stress across multiple dimensions rather than concentrating it at a single planar connection point.

The connection structure is divided into multiple discrete components: first metal layer segments, second metal layer segments, and connecting via segments. These segmented elements are distributed across the pad area and connected through vias, creating a web-like structure that disperses the mechanical and electrical load rather than relying on a single continuous metal trace.

The patent utilizes vertical stacking of metal layers to achieve ESD protection functionality within a reduced planar footprint. By arranging protective metal structures in multiple vertical layers connected through vias, the design provides comprehensive ESD protection coverage without proportionally increasing the chip's surface area.

The multi-layer metal web structure serves multiple functions simultaneously: it provides electrostatic discharge protection, maintains electrical connectivity, and distributes mechanical stress. This integrated structure eliminates the need for separate dedicated ESD protection elements that would increase chip area.