ESD Protection Modules with Resistive Network and Common Layer
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Solution Overview
Problem
Existing ESD protection technologies are inefficient in triggering for both weak and strong electrostatic discharges, often resulting in dead zones and overvoltage peaks due to inconsistent triggering and sizing of protection circuits.
Innovation Solution
A semiconductor device with multiple modules connected by a resistive network and a common semiconductor layer, each module sized for saturation during ESD, sharing excess current through a single triggering circuit to ensure fast and effective triggering of all modules, reducing the risk of dead zones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single large-sized triac protection circuit is used, then strong ESD discharges are absorbed effectively, but weak ESD discharges cannot be triggered rapidly
Solution Approach 1:
The protection device is divided into multiple protection modules (at least two), each containing a triggerable element. This segmentation allows each module to be optimized for different ESD strength levels, with smaller modules responding quickly to weak discharges and the system collectively handling strong discharges effectively.
2Speed
If several smaller ESD protection circuits are used, then weak ESD discharges are protected efficiently, but strong ESD pulses cannot be handled effectively due to inconsistent triggering
Solution Approach 1:
Multiple protection modules are merged into a single integrated device with shared components. The triggerable elements share a common semiconductor layer and are connected through resistive networks, ensuring coordinated operation and consistent triggering across all modules during strong ESD events.
3Device complexity
If triggerable elements have different anode-cathode distances, then device complexity is reduced, but dead zones appear between consecutive triggerings
Solution Approach 1:
Resistive networks are introduced as intermediary elements connecting the protection modules in series between the first and second terminals. These resistive networks ensure proper voltage distribution and sequential triggering of modules, eliminating dead zones by maintaining continuous protection coverage during ESD events.
4Reliability
If multiple protection modules are used, then coverage of different ESD strengths is improved, but device area increases
Solution Approach 1:
The protection modules are arranged in a nested or compact configuration where components are shared and optimized. The common semiconductor layer and shared resistive networks allow multiple protection functions to be integrated in a compact area, reducing the overall device footprint while maintaining comprehensive protection coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides rapid and effective protection against both weak and strong ESD discharges while minimizing the risk of module breakdown and overvoltages, allowing for compact design without the need for guard rings.
Implementation Method 1
The modules are connected between two terminals by the intermediary of a resistive network
Implementation Method 2
An electrostatic discharge (ElectroStatic Discharge: ESD) results, for example, in a current peak of 30 amps in one nanosecond followed by a current of 10 amps over 10 nanoseconds
Data Source
AI summary
A semiconductor device for protection from electrostatic discharge includes a number of modules for protection from electrostatic discharge. Each module includes a thyristor having terminals and a gate, and a diode coupled in antiparallel to the terminals of the thyristor. Each module is sized to share a saturation current with neighboring modules when an electrostatic discharge current is received. A resistive network couples modules between two terminals. A triggering circuit includes a common triggering output that is coupled to the gate of the thyristor of each module and a common buried semiconductor layer contacts each module.


