ESD Protection Circuit for Multi-Power Domain Interface
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Solution Overview
Problem
In multi-power domain semiconductor systems, interface circuits are susceptible to electrostatic discharge (ESD) damage due to ungrounded power supplies, which can degrade the gate oxide of NMOS and PMOS transistors, and existing ESD protection circuits fail to effectively manage different power voltage requirements.
Innovation Solution
A circuit design that includes multiple ESD clamp circuits and silicon-controlled rectifiers (SCRs) to maintain gate electrodes at a grounded voltage level during ESD events, using diodes and transistors to direct ESD currents and reduce voltage stress on transistors, and incorporating resistors and self-biased current trigger circuits to further protect against ESD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD clamp circuits are used in multi-power domain systems, then ESD protection is provided, but the gate oxide of NMOS and PMOS transistors is damaged due to ungrounded power supplies
Solution Approach 1:
The patent introduces an intermediary ESD protection circuit between the interface circuit and the ungrounded power supplies. This intermediary circuit includes clamp circuits and SCR devices that act as mediators to divert ESD current away from the gate electrodes, preventing direct damage while allowing normal signal operation to pass through.
Solution Approach 2:
The ESD protection is segmented into multiple independent domains, with separate ESD clamp circuits for each power domain (VDD1, VDD2, VSS1, VSS2). Each segment handles ESD events specific to its power domain, allowing localized protection without affecting other domains or the main interface circuit functionality.
2Adaptability or versatility
If multiple power supplies with different voltages are used to power separate sub-systems, then different power voltage requirements are met, but interface circuits become susceptible to ESD damage
Solution Approach 1:
The ESD protection circuit is designed with universal applicability across multiple power domains with different voltage levels. The clamp circuits and SCR devices are configured to universally handle ESD events regardless of which specific power domain (VDD1, VDD2, VSS1, VSS2) experiences the discharge, providing a unified protection mechanism for all interface circuits in the multi-power system.
3Reliability
If ESD clamp circuits are added to protect interface circuits, then ESD damage is prevented, but device complexity increases
Solution Approach 1:
Multiple ESD protection functions are merged into a single integrated circuit structure. The ESD clamp circuits for different power domains are combined with SCR devices and sharing common reference voltages where possible, reducing the overall component count and layout complexity compared to having completely separate protection circuits for each domain.
Solution Approach 2:
The ESD protection circuit is designed to be self-activating through the use of SCR (silicon-controlled rectifier) devices that automatically trigger when ESD voltage thresholds are exceeded. This self-service mechanism eliminates the need for external control signals or complex sensing circuits, simplifying the overall system while maintaining effective protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively protects interface circuits from ESD damage by maintaining voltage levels at gate electrodes near ground, reducing the risk of gate oxide damage and ensuring operation across various power voltage conditions.
Implementation Method 1
electrostatic discharge (ESD), which may damage or destroy the IC. ESD generally refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a relatively large amount of current passes through a part of the IC
Implementation Method 2
using diodes and transistors to direct ESD currents and reduce voltage stress on transistors
Data Source
AI summary
A circuit capable of providing electrostatic discharge (ESD) protection, the circuit comprising a first set of power rails comprising a first high power rail and a first low power rail, a first interface circuit between the first set of power rails, the first interface circuit having at least one gate electrode, a first ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, and a second ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, the first ESD device and the second ESD device being configured to maintain a voltage level at the at least one gate electrode of the first interface circuit at approximately a ground level when ESD occurs.