ESD Protection Circuit With Nested Wells And Drain Well
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional LDMOS devices used for ESD protection in high voltage processes exhibit poor characteristics such as strong snapback effect and base push out, which degrade their ESD performance and render integrated circuits defective.
Innovation Solution
A compact ESD protection device is designed with a specific transistor structure, including multiple doped wells and a drain well configuration that enhances ESD performance and latch-up immunity, featuring a gate with overlapping source/drain regions and a silicide block to prevent horizontal current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional LDMOS structure is used for ESD protection, then device simplicity is maintained, but ESD performance degrades due to strong snapback effect and base push out
Solution Approach 1:
The device is segmented into multiple functional regions including first and second device wells, third well, drain well, and multiple doped regions. This segmentation allows each region to perform specific functions that collectively improve ESD performance while managing the complexity through modular design
Solution Approach 2:
Different regions of the device are doped with different polarity types (first polarity and second polarity dopants) at different concentrations. The drain well extends below the gate with specific doping, and the third well is disposed within the second device well, creating local variations in electrical properties to control snapback effect and base push out
2Reliability
If drain well extends below the gate, then holding voltage increases improving ESD performance, but manufacturing complexity increases
Solution Approach 1:
The drain well is formed to extend below the gate in advance before final device assembly. The first and second device wells are disposed with specific geometries and doping profiles beforehand, allowing the structure to inherently provide the required holding voltage without requiring additional adjustment steps
Solution Approach 2:
The third well is nested within the second device well, which is itself disposed within the first device well. The drain well extends below the gate structure, creating a nested configuration that achieves the required holding voltage while consolidating multiple functions into a compact structure
Data Source
AI summary
A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region disposed adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well encompasses the device region and a second device well disposed within the first device well. The second device well encompasses the first diffusion region and at least a part of the gate. The device also includes a third well which is disposed within the second device well and a drain well which encompasses the second diffusion region and extends below the gate.