ESD Protection Circuit Latch-Up Immunity via Nested Wells
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Solution Overview
Problem
Traditional n-type lateral diffused metal oxide semiconductor (nLDMOS) devices suffer from 'strong snapback' characteristics, leading to latch-up issues during normal IC operation, which can render ICs defective.
Innovation Solution
The design incorporates an ESD protection circuit with specific transistor configurations and well structures, including first and second diffusion regions with dopants of a first polarity type, and second device wells disposed within a first device well, where a well contact surrounds the gates and abuts the first diffusion regions, directing current flow vertically to suppress snapback and enhance latch-up immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional nLDMOS structure is used, then device simplicity is maintained, but strong snapback characteristics occur leading to latch-up
Solution Approach 1:
The device is segmented into multiple functional regions: a first device well encompassing the device region, multiple second device wells disposed within the first device well, and a well contact that surrounds the gates. This segmentation allows independent control and optimization of different regions to suppress snapback while maintaining overall device functionality.
Solution Approach 2:
The patent implements a nested well structure where second device wells are disposed within the first device well, creating a multi-level nested configuration. The well contact further nests around the gates, surrounding them completely. This nested architecture enables precise control of electric fields in concentric zones to eliminate snapback characteristics.
2Reliability
If well contact surrounds gates and abuts first diffusion regions, then snapback is suppressed, but device area increases
Solution Approach 1:
The well contact serves multiple functions simultaneously: it provides electrical connection to the second device wells, surrounds and protects the gates, abuts the first diffusion regions to control electric fields, and contributes to suppressing snapback. This multi-functionality reduces the need for separate protective structures, optimizing area utilization.
Solution Approach 2:
The solution moves from planar protection methods to a three-dimensional well structure. The well contact extends vertically and surrounds the gates in multiple dimensions, providing ESD protection and snapback suppression through spatial configuration rather than increasing lateral footprint. This dimensional approach enables compact design with enhanced performance.
Data Source
AI summary
A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.