ESD Protection Circuit Using NMOS and Diode for Low Parasitic Capacitance
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Solution Overview
Problem
Conventional ESD protection circuits, particularly those using SCR, face challenges with high trigger voltage and large parasitic capacitance, which affect the reliability and efficiency of ESD protection for RF circuits, especially for RX pins with high operating voltage and signal swing, leading to potential damage and distortion.
Innovation Solution
A diode and MOS transistor-based ESD protection circuit is designed on a semiconducting substrate with strategically placed high doping concentration regions and a parasitic SCR structure, optimizing the layout to minimize parasitic capacitance and reduce trigger voltage, allowing for effective ESD current discharge through a bipolar transistor and MOSFET configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SCR is used for ESD protection, then high ESD capability is achieved, but trigger voltage becomes too high to operate
Solution Approach 1:
The SCR structure is segmented into two independent transistors (PNP and NPN) with separate triggering paths. The PNP transistor can be triggered by positive voltage at the trigger terminal, while the NPN transistor responds to negative voltage, allowing the protection circuit to operate at lower trigger voltages while maintaining high ESD capability through the combined action of both transistors.
Solution Approach 2:
The protection circuit is designed to handle multiple ESD modes (PS-mode, PD-mode, NS-mode, ND-mode) through a single unified structure. The dual-transistor SCR configuration provides universal protection across different electrostatic discharge scenarios, eliminating the need for separate protection circuits for each mode while maintaining low trigger voltage operation.
2Object-affected harmful factors
If MOS transistors are used for ESD protection, then low parasitic capacitance is achieved, but ESD capability becomes insufficient
Solution Approach 1:
The patent merges the advantages of MOS transistors (low parasitic capacitance) with the superior ESD capability of SCR structures. By integrating MOS triggering mechanisms with bipolar transistor discharge paths, the circuit achieves both low parasitic capacitance for high-speed signal integrity and high ESD capability for robust protection.
Solution Approach 2:
The protection circuit employs a composite structure combining different transistor types (MOS and bipolar) within a single integrated design. This composite approach leverages the complementary strengths of each transistor type to simultaneously achieve low parasitic capacitance and high ESD capability, resolving the contradiction between these two parameters.
3Reliability
If Lateral SCR is used for ESD protection, then high ESD capability is achieved, but trigger voltage remains high
Solution Approach 1:
The patent inverts the conventional LSCR triggering mechanism by introducing separate trigger terminals that apply voltage in opposite polarities to the respective transistor bases. This inversion allows the circuit to trigger at lower voltages by exploiting the natural turn-on characteristics of bipolar transistors rather than relying on the high-voltage breakdown mechanism of conventional LSCR.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a low parasitic capacitance, wide operating voltage range, and high ESD capability, effectively protecting RF circuits from ESD damage while maintaining low trigger voltage and minimizing signal distortion.
Implementation Method 1
ESD protection circuit
Implementation Method 2
total parasitic capacitance of connection pins between the circuit and ESD protection circuit must be smaller than 200 fF
Data Source
AI summary
The present invention discloses an electrostatic discharge protection circuit, comprising a diode and a N-type metal-oxide-semiconductor (NMOS) transistor. The diode locating on a N-well comprises an high P-doping concentration region and an nonadjacent high N-doping concentration region. The NMOS transistor, locating on a P-well, comprises a drain, a source and a gate, and the drain and the source are formed by the high N-doping concentration region. Wherein the P-well further comprises a high P-doping concentration region near the source, the drain of the NMOS is electrically connected to the high N-doping concentration region of the diode, the source of the NMOS and the adjacent high P-doping concentration region are electrically connected to a ground, the gate of the NMOS transistor electrically connected to a trigger point. Accordingly, the electrostatic discharge protection circuit has a low parasitic capacitance, wide operating voltage range and high electrostatic discharge (ESD) capability for resolving the problems about the ESD of the RX pins.