High Voltage ESD Protection Apparatus with Segmented NPN Circuits

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Solution Overview

Problem

Conventional ESD protection circuits for semiconductor devices often fail to provide adequate protection against high voltage spikes, leading to potential damage from electrostatic discharge (ESD) due to limitations in breakdown voltage and current handling.

Innovation Solution

An NPN transistor-based ESD protection device is designed with a diode and NPN transistor in series, utilizing shallow p-type and n-type wells, and p-type metal contacts to enhance breakdown voltage and provide a reliable discharge path for ESD current, thereby protecting internal circuits from voltage spikes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ESD protection circuits are used, then basic ESD protection is provided, but they fail to provide adequate protection against high voltage spikes due to limitations in breakdown voltage and current handling

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidvoltage spike damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The ESD protection circuit is divided into multiple functional segments: a first ESD protection circuit connected to the power bus, a second ESD protection circuit connected to the output node, and a switching mechanism. This segmentation allows each circuit to specialize in protecting against different types of voltage spikes, with the first circuit handling power bus ESD events and the second circuit handling output node ESD events, thereby providing comprehensive protection against high voltage spikes that a single circuit cannot handle alone.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic switching between different ESD protection circuits based on the detected ESD event characteristics. A switching mechanism selectively activates the first ESD protection circuit for power bus ESD events and the second ESD protection circuit for output node ESD events. This dynamic adaptation allows the system to optimize its protection response according to the specific ESD threat, thereby reliably protecting against high voltage spikes across different scenarios.

Inventive Principle:
Principle #15Dynamics

2Reliability

If a single ESD protection circuit is used, then device complexity is reduced, but it cannot simultaneously protect against both power bus ESD events and output node ESD events with high breakdown voltage

Engineering Contradiction:
Improvecomprehensive ESD protectionVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protection system is segmented into two specialized ESD protection circuits: the first circuit is optimized for power bus ESD events with appropriate breakdown voltage characteristics, while the second circuit is optimized for output node ESD events. This segmentation allows each circuit to be independently optimized for its specific protection target, achieving comprehensive ESD protection without requiring a single overly complex circuit design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A switching mechanism acts as an intermediary between the two ESD protection circuits and the ESD detection system. This intermediary selectively connects the appropriate protection circuit based on the detected ESD event type, coordinating the operation of multiple circuits in a controlled manner. The switching mechanism manages the complexity by providing a systematic way to activate only the necessary protection circuit, thereby achieving comprehensive protection with controlled device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If breakdown voltage is increased to protect against high voltage spikes, then protection capability is improved, but current handling capability may be reduced

Engineering Contradiction:
Improvebreakdown voltage protectionVSAvoidcurrent handling capability
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent segments the ESD protection function into two circuits with different breakdown voltage characteristics. The first ESD protection circuit has a higher breakdown voltage threshold optimized for power bus protection, while the second ESD protection circuit has a lower breakdown voltage threshold optimized for output node protection with better current handling. This segmentation allows the system to achieve both high breakdown voltage protection and adequate current handling capability by distributing these functions across specialized circuits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The switching mechanism dynamically selects which ESD protection circuit to activate based on the detected ESD event characteristics. When a power bus ESD event is detected, the first circuit with higher breakdown voltage is activated. When an output node ESD event is detected, the second circuit with better current handling is activated. This dynamic selection ensures that the system maintains both high breakdown voltage protection and adequate current handling capability by using the appropriate circuit for each specific ESD threat.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively increases the breakdown voltage and provides a reliable current discharge path, effectively preventing damage from ESD events by clamping voltage levels below the maximum rating, thus ensuring the integrity of semiconductor devices.

Implementation Method 1

utilizing shallow p-type and n-type wells, and p-type metal contacts to enhance breakdown voltage and provide a reliable discharge path for ESD current

Methodology Applied
Scientific EffectBreakdown voltage: Avalanche Breakdown

Data Source

PatentUS20220165725A1High Voltage ESD Protection Apparatus
Publication Date: 2022.05.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20220165725A1 patent drawing
  • US20220165725A1 patent drawing
  • US20220165725A1 patent drawing

AI summary

A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.