ESD Protection Circuit for Output Transistors
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Solution Overview
Problem
Integrated circuits, especially CMOS circuits, are susceptible to electro-static discharge (ESD) failures due to human and mechanical handling, as existing ESD protection circuits often fail to prevent the output NMOS from turning on during ESD events, leading to potential damage and increased leakage, and occupy valuable chip area.
Innovation Solution
A detection circuit that receives ESD voltage stress from the +Vdd power rail, transfers it through a capacitor to an inverter, and combines with the OE signal to keep output transistors off during ESD events, using an RC combination to differentiate the signal and activate the inverter, thus preventing the NMOS from turning on and reducing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ESD protection circuits with switches on each output are used, then ESD protection is provided, but chip area is occupied and transients may cause noise in adjacent outputs
Solution Approach 1:
The patent merges multiple ESD protection functions into a single shared detection circuit that protects all outputs collectively. Instead of having separate protection circuits for each output, one detection circuit monitors the common Vdd rail and controls all output transistors simultaneously, eliminating the need for individual switches on each output and reducing chip area occupation.
Solution Approach 2:
The detection circuit serves multiple outputs universally by monitoring the common power rail and controlling all output transistors through a shared control line. This multi-functional approach allows a single circuit to protect multiple outputs from ESD events, reducing overall chip area while maintaining comprehensive protection.
2Object-affected harmful factors
If output NMOS is allowed to discharge ESD events, then voltage spike reduction occurs, but NMOS may enter snap-back condition and fail or exhibit increased leakage
Solution Approach 1:
The detection circuit detects ESD voltage spikes on the Vdd rail before they can cause the output NMOS to turn on and enter snap-back conditions. By detecting the ESD event early and preemptively turning off the output transistors, the circuit prevents the harmful snap-back effect while still allowing the primary ESD protection devices to discharge the voltage spike safely.
Solution Approach 2:
The detection circuit continuously monitors the Vdd rail for ESD voltage spikes and provides feedback control to the output transistors. When an ESD event is detected, the circuit immediately responds by turning off the output transistors, creating a feedback loop that prevents snap-back conditions while maintaining normal operation during non-ESD conditions.
3Object-affected harmful factors
If primary ESD protection devices are used, then ESD voltage limitation is achieved, but output NMOS may still turn on and interfere with protection operation
Solution Approach 1:
The detection circuit performs preliminary detection of ESD events on the Vdd rail before the output NMOS can turn on and interfere with the primary ESD protection devices. By detecting the ESD voltage spike early and preemptively turning off the output transistors, the circuit ensures that the primary ESD protection devices can operate effectively without interference from the output NMOS.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively protects output transistors from ESD stress without direct contact, reducing chip area usage and preventing snap-back conditions, increasing ESD tolerance from 1 kV to 4 kV and eliminating leakage, while ensuring primary ESD protection devices handle the stress.
Implementation Method 1
transfers it through a capacitor to the input of an inverter
Implementation Method 2
using an RC combination to differentiate the signal and activate the inverter
Data Source
AI summary
An ESD protection circuit is described that protects the output transistors of a target circuit, usually an integrated circuit, that has an output enable, OE, or similar control input. An OE signal turns off the output transistors allowing the target circuit output, or outputs, to electrically float. Such a condition is commonly called a three state condition. The inventive protection circuit is not connected to the output directly, it senses an ESD voltage spike at the +Vdd contact to the circuit and produces a timed signal. The timed signal is converted to logic levels and gated with the OE signal (that the system previously provided to the OE control input). The output of gate forms a new OE control input signal that forces the target circuit into its three state condition during the period of the timed signal.