ESD Protection Apparatus with Parasitic Resistance Delay Circuit
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Solution Overview
Problem
As CMOS technologies approach the nanometer scale, the breakdown voltage of the gate oxide layer decreases, leading to increased leakage currents, which complicates ESD protection circuit designs and requires a low leakage current ESD clamp circuit to effectively manage electrostatic discharge.
Innovation Solution
An ESD protection apparatus is designed with a clamp circuit and a detection circuit, where parasitic resistances and an electronic element form a delay circuit to provide a drive voltage and trigger current for conducting the clamp circuit during an ESD event, while minimizing leakage current during normal operation by disconnecting the discharge path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate oxide layer is made thinner to approach nanometer scale CMOS technology, then the breakdown voltage decreases and manufacturing precision improves, but the leakage current increases significantly
Solution Approach 1:
The detection circuit is designed to detect ESD events before they cause damage to the thin gate oxide layer. By preliminarily detecting voltage changes on the power rails, the system can activate protection mechanisms in advance, preventing harmful leakage currents from affecting the already-vulnerable thin oxide layer during normal operation.
Solution Approach 2:
The patent introduces a detection circuit as an intermediary between the power rails and the clamp circuit. This intermediary detects ESD events and triggers the clamp circuit appropriately, ensuring that the thin gate oxide layer is protected without requiring the clamp circuit to be constantly active, thereby minimizing leakage current while maintaining protection capability.
2Reliability
If the clamp circuit is continuously active to provide ESD protection, then reliability improves, but leakage current between power rails increases
Solution Approach 1:
The clamp circuit is designed to be dynamic rather than static. It remains inactive during normal operation to minimize leakage current and only becomes active when the detection circuit identifies an ESD event. This dynamic behavior maintains reliability by providing protection when needed while minimizing harmful leakage current during normal operation.
Solution Approach 2:
The detection circuit provides feedback about the state of the power rails to the clamp circuit. When the detection circuit detects an ESD event through voltage changes, it triggers the clamp circuit to activate. This feedback mechanism ensures the clamp circuit is only active when necessary, maintaining reliability while minimizing leakage current during normal operation.
3Reliability
If the detection circuit is added to detect ESD events, then ESD protection reliability improves, but device complexity increases
Solution Approach 1:
The detection circuit is designed to perform multiple functions: detecting ESD events, determining their severity, and triggering appropriate responses in the clamp circuit. By making the detection circuit multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby improving ESD protection reliability while minimizing the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The apparatus effectively reduces leakage current during normal operation and provides a reliable discharge path during ESD events, enhancing ESD protection and power performance by ensuring the clamp circuit is only activated when necessary.
Implementation Method 1
The electronic element has two terminals respectively coupled to the first node and the second rail line, and has an equivalent capacitance value
Implementation Method 2
multiple leakage currents correspondingly pass between a first input and a gate and between a second input and the gate of the transistor, and respectively form a first parasitic resistance and a second parasitic resistance
Data Source
AI summary
An electrostatic discharge (ESD) protection apparatus, coupled between a first rail line and a second rail line, includes a clamp circuit and a detection circuit. The detection circuit includes an electronic element having an equivalent capacitance value, and a transistor having a gate, a first input and a second input respectively coupled to a first node, the first rail line and a drive terminal of the clamp circuit. In response to an ESD event, leakage currents pass between the first input and the gate and between the second input and the gate to equivalently form parasitic resistance therein, respectively. The parasitic resistances and the electronic element form a delay circuit to provide a drive voltage between the gate and the first input, and to provide a trigger current for conducting the clamp circuit, so that the first and second rail lines perform an ESD operation via the clamp circuit.