Bidirectional ESD Protection via PBL Relocation
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Solution Overview
Problem
Conventional bidirectional silicon-controlled rectifier (SCR)-based ESD protection devices with a p-type buried layer (PBL) under the merged drains suffer from leakage due to punch-through between terminals, which is not present in unidirectional SCRs, and struggle to maintain high breakdown voltage while providing adequate current conduction during ESD events.
Innovation Solution
The PBL is positioned under the source terminals instead of the drains, eliminating leakage and maintaining high breakdown voltage by controlling current flow paths, and this layout change does not require altering process parameters that could affect other IC components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a PBL is placed under the merged drains to increase breakdown voltage, then breakdown voltage is improved, but leakage current increases due to punch-through between terminals
Solution Approach 1:
The patent extracts the PBL from its conventional position under the merged drains and relocates it to the substrate beneath the device. This separation removes the source of punch-through leakage (the PBL under drains) while preserving the high breakdown voltage capability through alternative structural design. The PBL is completely removed from the drain region to eliminate the leakage path.
Solution Approach 2:
The patent moves the PBL from a two-dimensional position under the drains to a three-dimensional position in the substrate below the entire device structure. This spatial relocation in the vertical dimension eliminates the lateral punch-through path between terminals while maintaining the voltage blocking function through the substrate's inherent properties.
2Adaptability or versatility
If two SCRs are provided in parallel for bidirectional protection, then bidirectional ESD protection is achieved, but current flow paths become difficult to isolate during IEC strikes
Solution Approach 1:
The patent introduces an n-type substrate as an intermediary element between the two SCRs. This substrate acts as a current path separator that prevents cross-conduction during IEC strikes. The substrate's inherent electrical properties create natural isolation barriers that guide current flow through defined paths, eliminating the complexity of isolating parallel SCR current paths.
3Strength
If remote drain MOS devices with PBL under drains are used, then high breakdown voltage is achieved, but inherent ESD protection becomes poor
Solution Approach 1:
The patent inverts the conventional design approach by removing the PBL from under the drains (where it causes ESD vulnerability) and relocating it to the substrate (where it provides voltage blocking). This inversion transforms the PBL from a harmful element in the drain region to a beneficial element in the substrate, simultaneously achieving high breakdown voltage and improved ESD protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces or eliminates leakage and maintains high breakdown voltage, enhancing the robustness of bidirectional SCR-based ESD protection devices without altering process parameters, thus improving their performance compared to conventional designs with PBL under the merged drains.
Implementation Method 1
leakage due to punch-through between terminals
Implementation Method 2
The PBL is positioned under the source terminals instead of the drains, eliminating leakage and maintaining high breakdown voltage by controlling current flow paths
Implementation Method 3
Bidirectional electrostatic discharge (ESD) protection
Implementation Method 4
ESD protection devices generally operate by providing a high capacity current conduction path, so that the brief but massive ESD charge may be safely conducted away
Data Source
AI summary
A bidirectional electrostatic discharge (ESD) protection device includes a substrate having a topside semiconductor surface that includes a first silicon controlled rectifier (SCR) and a second SCR formed therein including a patterned p-buried layer (PBL) including a plurality of PBL regions. The first SCR includes a first and second n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a first merged drain. The second SCR includes a third and a fourth n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a second merged drain. The plurality of PBL regions are directly under at least a portion of the sources while being excluded from being directly under either of the merged drains.