ESD Protection Semiconductor Device Using Segmented PNPN Structures

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Solution Overview

Problem

Existing semiconductor devices face challenges in effectively protecting against electrostatic discharge (ESD) due to high trigger voltage and insufficiently fast turn-on speed, which can cause damage to semiconductor wafers during ESD events.

Innovation Solution

A semiconductor device with a modified PNPN structure, including deep N-type and P-type regions, and a detective circuit that detects trigger voltage at the protected terminal, allowing for faster and more reliable ESD protection by connecting the voltage to a ground terminal through a route structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional PNPN structure is used for ESD protection, then the device can provide basic ESD protection function, but the trigger voltage is too high and the turn-on speed is insufficiently fast

Engineering Contradiction:
ImproveESD protection effectivenessVSAvoidturn-on speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The conventional single PNPN structure is segmented into multiple nested PNPN structures (first PNPN structure and second PNPN structure). The first PNPN structure triggers at a lower voltage threshold and activates the second PNPN structure, creating a staged response that achieves faster overall turn-on while maintaining appropriate trigger voltage levels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A second PNPN structure is nested within the first PNPN structure, with the second structure's P-type well positioned within the N-type well of the first structure. This nested configuration allows the inner structure to be activated by the outer structure, creating a cascaded trigger mechanism that improves response speed.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If a conventional PNPN structure is used for ESD protection, then the device can provide basic ESD protection function, but the trigger voltage is too high causing delayed response

Engineering Contradiction:
ImproveESD protection effectivenessVSAvoiddamage from ESD events
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The ESD protection function is divided between two PNPN structures with different trigger characteristics. The first structure provides initial detection and triggering at lower voltage, while the second structure handles the main current diversion, collectively achieving lower effective trigger voltage and faster response to prevent ESD damage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first PNPN structure acts as a preliminary trigger mechanism that activates before the main ESD current peak occurs. By detecting the rising voltage edge and pre-triggering the protection path, the system prepares the low-impedance path in advance, reducing the effective trigger voltage threshold and preventing damage.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables faster and more reliable ESD protection by reducing the trigger voltage and ensuring efficient current flow to ground, thereby preventing damage from ESD events.

Implementation Method 1

The ESD device is based on silicon-controlled rectifier (SCR) mechanism

Methodology Applied
Scientific EffectSCR mechanism:

Implementation Method 2

A first heavily doped P-type region in the first P-type well, to also connect to the protected terminal. A first heavily doped N-type region is in the second N-type well, to serve as a ground terminal to receive the ground voltage

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS11257807B2Semiconductor device of electrostatic discharge protection
Publication Date: 2022.02.22 UNITED MICROELECTRONICS CORP
  • US11257807B2 patent drawing
  • US11257807B2 patent drawing
  • US11257807B2 patent drawing

AI summary

A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.