ESD Protection Element Using Potential Increasing Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing ESD protection circuits face a trade-off between increasing the drive current of the power clamp MOS transistor and reducing off-state leakage, which leads to increased current consumption during normal operations.
Innovation Solution
Incorporating a diode between the source of the clamp MOS transistor and the ground line to increase the potential of the source, thereby reducing off-state leakage while ensuring sufficient drive current during ESD operations, along with a resistive and capacitive element and a CMOS inverter to manage the discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate length is decreased or the gate width is increased to increase the drive current of the power clamp MOS transistor, then the discharge ability of the ESD protection circuit is enhanced, but off-state leakage increases leading to higher current consumption during normal operations
Solution Approach 1:
The invention changes the potential parameter of the diffusion layer at the ground line side by introducing a potential increasing circuit. This circuit raises the potential of the diffusion layer above the ground line potential, which modifies the electric field distribution in the MOS transistor channel. This parameter change allows the transistor to maintain higher drive current during ESD events while reducing off-state leakage during normal operation, as the elevated diffusion layer potential creates a more favorable condition for charge carrier control without requiring physical dimension changes
2Reliability
If the size of the MOS transistor is increased to increase the drive current, then the ESD protection capability is improved, but the device area increases and off-state leakage increases
Solution Approach 1:
Instead of increasing the physical dimensions of the MOS transistor to improve ESD protection capability, the invention changes the electrical parameter (potential) of the diffusion layer. By elevating the diffusion layer potential above ground potential through the potential increasing circuit, the invention achieves enhanced ESD protection capability without increasing the transistor area, as the improved protection comes from electrical field modification rather than physical size increase
3Productivity
If the gate length is decreased to increase the drive current, then the discharge ability is enhanced, but the manufacturing precision requirements increase and off-state leakage increases
Solution Approach 1:
The invention avoids the need to decrease gate length to improve discharge ability. Instead, it changes the potential parameter of the diffusion layer through the potential increasing circuit. This approach enhances discharge ability without imposing stricter manufacturing precision requirements on the gate length, as the improvement is achieved through electrical parameter modification rather than physical dimension reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces off-state leakage current while maintaining a sufficient drive current during ESD operations, thereby minimizing power consumption and enhancing the ESD protection circuit's efficiency.
Implementation Method 1
a potential increasing circuit that increases a potential of a diffusion layer at the ground line side of the clamp MOS transistor, more than a potential of the ground line
Data Source
AI summary
To provide a protection element in which an increase in current due to off-state leakage can be reduced while a drive current can be ensured during an ESD operation.Provided is the protection element including: a clamp MOS transistor that has a drain coupled to a power supply line and a source coupled to a ground line; and a potential increasing circuit that increases a potential of a diffusion layer at the ground line side of the clamp MOS transistor, more than a potential of the ground line. In this protection element, the potential of the diffusion layer coupled to the ground line of the clamp MOS transistor is increased from the potential of the ground line, whereby an increase in current due to off-state leakage can be reduced while a sufficient drive current is ensured during an ESD operation.