ESD Protection Apparatus with Ring-Shaped Doping for Parasitic SCR Holding Voltage
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Solution Overview
Problem
Parasitic silicon controlled rectifiers (SCRs) in semiconductor ICs have a holding voltage lower than their trigger voltage, leading to electrical overstress (EOS) and latch-up risks during high-voltage operations, and increasing the distance between anode and cathode to mitigate this enlarges the IC layout, contradicting the trend of scaling down semiconductor devices.
Innovation Solution
An ESD protection apparatus is designed with a semiconductor substrate featuring four doping regions in two wells of different conductivities, forming NPN and PNP parasitic BJTs and a parasitic SCR, where one doping region is surrounded by a ring-shaped region with opposite conductivity, allowing the ring-shaped region to be subjected to a higher voltage during normal operation to increase the holding voltage of the parasitic SCR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between anode and cathode of parasitic SCR is elongated to increase holding voltage, then the holding voltage is improved, but the layout size of semiconductor IC is increased
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping concentration distribution within the SCR structure. Specifically, it uses a gradient doping profile where the doping concentration varies spatially - higher near the anode and lower near the cathode - to locally enhance the electric field distribution. This localized doping variation increases the holding voltage without requiring an increased physical distance between anode and cathode, thus resolving the contradiction between reliability improvement and layout size constraint.
Solution Approach 2:
The patent employs parameter changes by modifying the doping concentration parameter throughout the SCR structure. By adjusting the doping concentration gradient and creating different doping levels in different regions (such as the n-type and p-type regions), the holding voltage parameter is enhanced. This allows the device to achieve higher holding voltage within the same physical dimensions, effectively resolving the contradiction between improved reliability and maintained compact layout.
2Reliability
If parasitic SCR is used for ESD protection, then current sinking capability is improved, but EOS or latch up risk occurs during high-voltage operation
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the SCR with a gradient doping profile that anticipates and prevents the harmful latch-up effect during high-voltage operation. The non-uniform doping distribution is designed beforehand to create a controlled electric field that allows the SCR to sink ESD current effectively while maintaining a higher holding voltage threshold. This preliminary structural arrangement prevents the harmful latch-up condition from occurring, while preserving the beneficial current sinking capability.
Solution Approach 2:
The patent uses local quality by creating regions with different doping concentrations within the SCR structure. The gradient doping profile creates local variations in electrical properties that enable the device to differentiate between normal ESD current (which needs to be sunk) and conditions that would lead to harmful latch-up. The localized high-doping regions near the anode and lower-doping regions near the cathode work together to maintain current sinking capability while preventing harmful effects during high-voltage operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly increases the holding voltage of the parasitic SCR, reducing the risk of EOS and latch-up while maintaining a compact IC layout, with the holding voltage ranging from 5V to 6V compared to conventional devices.
Implementation Method 1
The first doping region having the second conductivity is disposed in the first well. The second doping region having the first conductivity is at least partially disposed in the first well and surrounds the first doping region. The third doping region having the first conductivity is disposed in the second well and adjacent to the second doping region. The fourth doping region having the second conductivity is disposed in the second well and adjacent to the third doping region.
Data Source
AI summary
An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region and a fourth doping region. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the second conductivity is disposed in the first well. The second doping region having the first conductivity is at least partially disposed in the first well and surrounds the first doping region. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The first doping region, the third doping region, the first well and the second well are integrated to form a first parasitic BJT and a second parasitic BJT that have different majority carriers.