ESD Protection Device Using SCR and Control Circuit
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Solution Overview
Problem
Conventional ESD protection devices for semiconductor integrated circuits face challenges in maintaining high triggering and holding voltages during normal operation while achieving low triggering and holding voltages during ESD events without increasing the circuit area, which is costly due to the need for additional guard rings and control circuits.
Innovation Solution
An ESD protection device incorporating a silicon controlled rectifier (SCR) with a diode structure, where the control circuit manages voltage to the diode in normal and ESD modes, allowing the SCR to be turned off during normal operation and on during ESD events, utilizing an N-type metal oxidation semiconductor (NMOS) transistor and bipolar junction transistors to discharge electrostatic charges without the need for guard rings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If guard rings and control circuits are added to the ESD protection circuit, then the triggering voltage and holding voltage can be controlled to be higher during normal operation and lower during ESD events, but the circuit area is enlarged and manufacturing cost increases
Solution Approach 1:
The patent merges the ESD protection function with the normal operation function into a single integrated circuit structure. The snapback element serves dual purposes: protecting against ESD events while also functioning as part of the normal circuit operation, eliminating the need for separate guard rings and control circuits.
Solution Approach 2:
The snapback element is designed to perform multiple functions: it provides ESD protection during electrostatic events and simultaneously operates during normal circuit function. This multi-functional design replaces the need for dedicated ESD protection components like guard rings, reducing overall circuit area.
2Reliability
If guard rings and control circuits are added to the ESD protection circuit, then the triggering voltage and holding voltage can be controlled to be higher during normal operation and lower during ESD events, but the manufacturing cost increases
Solution Approach 1:
The patent merges the ESD protection function with the normal operation function into a single integrated circuit structure. The snapback element serves dual purposes: protecting against ESD events while also functioning as part of the normal circuit operation, eliminating the need for separate guard rings and control circuits.
Solution Approach 2:
The patent uses a simple snapback element structure that can be easily manufactured using standard semiconductor fabrication processes. This approach replaces complex guard ring structures with a more economical design that achieves the same ESD protection function at lower manufacturing cost.
3Reliability
If the snapback element is triggered during normal high-voltage operation, then the holding voltage is lower than the normal input high voltage, but the snapback element is damaged
Solution Approach 1:
The patent utilizes the dynamic parameter changes of the snapback element, specifically the snapback effect where the voltage drops from a higher state to a lower holding state after triggering. This parameter change allows the element to safely dissipate ESD energy while protecting the circuit during normal operation.
Solution Approach 2:
The patent converts the potentially harmful snapback effect, which could damage the element during normal operation, into a beneficial ESD protection mechanism. By designing the circuit to utilize the snapback voltage drop, the element safely dissipates electrostatic energy while protecting the broader circuit from damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively provides high triggering and holding voltages during normal operation and low voltages during ESD events, enhancing ESD protection without enlarging the circuit area, thus reducing manufacturing costs and preventing semiconductor damage.
Implementation Method 1
The ESD occurs for an extremely short period of time, which is only within the level of several nano-seconds (ns). A very high current is generated in the ESD event
Implementation Method 2
the snapback element 100, such as an N-type metal oxidation semiconductor (NMOS) transistor, has a drain electrically connected to a pad 10
Data Source
AI summary
An ESD protection device for a pad includes an adjusting circuit, a snapback element and a control circuit. The adjusting circuit includes a silicon controlled rectifier (SCR) coupled to the pad. The SCR includes a first diode. The snapback element is coupled to a first N pole of the first diode when a second diode is not used, and is coupled to a second N pole of the second diode when the second diode is used. The control circuit is coupled to the first N pole. In a normal operation mode, the control circuit provides a first voltage to the first N pole so that the first N pole collects a plurality of charges and the SCR is turned off. In an ESD mode, the control circuit does not provide the first voltage to the first N pole so that the first N pole does not collect the charges.