ESD Protection Device With Segmented Diffusion Regions
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Solution Overview
Problem
Existing semiconductor devices with single gate electro-static discharge protection circuits face challenges in maintaining consistent AC characteristics due to variations in the resistance of the ballast resistor, leading to potential damage from ESD surges before the protection circuit fully operates, which increases development costs and time.
Innovation Solution
The formation of a p+ diffusion region below the drain electrode with controlled impurity concentration and dimensions, overlapping the n+ diffusion region, creates a narrower depletion layer, allowing the parasitic bipolar transistor to conduct at a lower voltage, thereby stabilizing the ballast resistor resistance and ensuring consistent AC characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p+ diffusion region is formed in the drain region at a deep portion of the substrate to enhance ESD robustness, then ESD protection capability is improved, but AC characteristics vary during normal operation depending on the accuracy of the diffusion region formation process
Solution Approach 1:
The invention divides the diffusion region into two separate regions: an n+ diffusion region formed at a shallow portion of the substrate and a p+ diffusion region formed at a deep portion. This segmentation allows independent optimization of each region's formation process, reducing the impact of process variations on overall device characteristics and improving both ESD robustness and AC characteristics consistency.
2Device complexity
If a single gate electro-static discharge element is used to protect input/output circuits, then device structure is simplified, but the protection circuit may not operate quickly enough before ESD damage occurs
Solution Approach 1:
The invention creates different local conditions within the electro-static discharge element by forming the n+ diffusion region at a shallow portion and the p+ diffusion region at a deep portion. This local quality differentiation enables the parasitic bipolar transistor to activate at lower voltages through the shallow n+ region, improving protection response speed while maintaining the simple single-gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the semiconductor device to operate effectively at a lower voltage, improving ESD robustness and reducing the need for repeated circuit simulations, thus lowering development costs and time by maintaining consistent AC characteristics.
Implementation Method 1
creates a narrower depletion layer, allowing the parasitic bipolar transistor to conduct at a lower voltage
Implementation Method 2
The formation of a p+ diffusion region below the drain electrode with controlled impurity concentration and dimensions, overlapping the n+ diffusion region
Data Source
AI summary
An electro-static discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first silicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode.