ESD Protection Circuit Series Transistor Segmentation
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Solution Overview
Problem
Existing ESD protection circuits face challenges in accurately modeling breakdown conduction, leading to inefficient design and increased leakage current, and suffer from layout inefficiencies and high parasitic capacitance, particularly when using thin gate-oxide transistors for protection.
Innovation Solution
An ESD protection circuit utilizing a series topology of transistors with a resistor and protection transistors, where each transistor has a gate coupled to its drain, and the resistor is between an internal node and a signal node, allowing for channel conduction-based protection with transistors of varying gate-oxide thickness to manage ESD current effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thin gate-oxide transistors are used for ESD protection, then ESD protection capability is improved, but leakage current increases and parasitic capacitance increases
Solution Approach 1:
The protection transistor is divided into multiple segments: a first transistor with thin gate-oxide for ESD protection and a second transistor with thick gate-oxide for low leakage, connected in series between the internal node and voltage node. This segmentation allows each transistor to be optimized for its specific function.
Solution Approach 2:
Different regions of the circuit use transistors with different gate-oxide thicknesses tailored to local requirements. The first transistor uses thin gate-oxide where high ESD protection is needed, while the second transistor uses thick gate-oxide where low leakage is critical.
2Reliability
If thin gate-oxide transistors are used for ESD protection, then ESD protection capability is improved, but parasitic capacitance increases affecting signal transmission speed
Solution Approach 1:
The protection path is segmented into two transistors in series, where only the first transistor has thin gate-oxide for ESD protection. The second transistor has thick gate-oxide contributing minimal parasitic capacitance to the signal path, thus maintaining signal transmission speed.
3Reliability
If breakdown conduction model is used for transistor protection, then design complexity increases due to inaccurate modeling, but protection effectiveness may be compromised
Solution Approach 1:
The invention converts the harmful breakdown conduction mode into a beneficial channel conduction mode by using a series transistor configuration. The first transistor operates in channel conduction mode during normal protection, avoiding the inaccuracies of breakdown modeling while still providing effective ESD protection.
4Reliability
If series topology with multiple transistors is used, then ESD protection effectiveness is improved, but device complexity increases
Solution Approach 1:
The protection function is segmented into two specialized transistors working in series, each optimized for specific aspects of ESD protection. This segmentation improves overall protection effectiveness while maintaining manageable circuit complexity through clear functional division.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces trigger voltage, minimizes parasitic capacitance, enhances layout efficiency, and provides flexible design parameters to adapt to different applications, ensuring rapid and effective ESD protection without compromising signal transmission speed.
Implementation Method 1
the node ni is conducted to the node nv2 by breakdown conduction of the transistor N0 if the voltage V_ESD is positive (with respect to the node nv2) or by conduction of a forward-biased parasitic diode of the transistor N0 if the voltage V_ESD is negative
Implementation Method 2
by conduction of a forward-biased parasitic diode of the transistor N0 if the voltage V_ESD is negative
Data Source
AI summary
ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate.