ESD Protection Circuit With Shared Signal Tap Regions

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Solution Overview

Problem

The miniaturization of integrated circuits has increased their susceptibility to electrostatic discharge (ESD) events due to thinner dielectric thicknesses and lower dielectric breakdown voltages, leading to potential electronic circuit damage.

Innovation Solution

An ESD protection circuit is implemented, comprising a first diode, a second diode, and an ESD clamp circuit, where the diodes share signal tap regions with the ESD clamp circuit, reducing area occupation and signal taps, resulting in lower resistance and faster operation compared to other approaches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the dielectric thickness is reduced to enable miniaturization, then the device size and power consumption are improved, but the dielectric breakdown voltage decreases making the device more susceptible to ESD damage

Engineering Contradiction:

Improvedevice sizeVSAvoidESD susceptibility

Core Design Contradiction:

Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

The ESD protection circuit is segmented into multiple functional components: a first diode for initial ESD clamping, a second diode for additional protection, and an ESD clamp circuit with signal tap regions for enhanced control. This segmentation allows each component to handle specific aspects of ESD protection, providing comprehensive protection despite reduced dielectric thickness

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The ESD protection circuit performs preliminary action by proactively clamping ESD events before they can cause damage to the thin dielectric structures. The diodes and clamp circuit are positioned to intercept ESD current paths in advance, diverting harmful energy away from vulnerable miniaturized components

Inventive Principle:

Principle #10Preliminary action

2Reliability

If separate signal tap regions are provided for each diode, then the ESD protection coverage is improved, but the area occupation and number of signal taps increase

Engineering Contradiction:

ImproveESD protection coverageVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The first diode and second diode are configured to share common signal tap regions with the ESD clamp circuit. This merging of signal tap resources reduces the total number of separate taps required, decreasing area occupation while maintaining comprehensive ESD protection coverage through coordinated operation of shared components

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared signal tap regions serve multiple functions: they provide ESD clamping for the first diode, protection for the second diode, and control signals for the ESD clamp circuit simultaneously. This multi-functionality allows a single signal tap infrastructure to support comprehensive ESD protection across multiple protection paths

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If more signal taps are used to improve ESD protection, then the protection effectiveness is improved, but the resistance increases and operation speed decreases

Engineering Contradiction:

ImproveESD protection effectivenessVSAvoidoperation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

By merging the signal tap infrastructure, the circuit reduces the total number of discrete tap connections required. Fewer signal taps mean lower cumulative resistance in the ESD protection path, enabling faster ESD response and clamping operation while maintaining comprehensive protection effectiveness

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The ESD protection circuit effectively mitigates ESD events by providing a lower clamping voltage and faster operation, reducing the risk of circuit damage while occupying less area and having fewer signal taps.

Implementation Method 1

electrostatic discharge (ESD) events

Methodology Applied

Scientific EffectElectrostatic discharge: Electrostatic Discharge

Implementation Method 2

a first diode, a second diode and an ESD clamp circuit. The first diode is in a semiconductor wafer, and is coupled to an input output (IO) pad

Methodology Applied

Scientific EffectDiode conduction: Diode

Implementation Method 3

providing a lower clamping voltage and faster operation, reducing the risk of circuit damage

Methodology Applied

Scientific EffectVoltage clamping:

Data Source

PatentUS11626719B2Electrostatic discharge (ESD) protection circuit and method of operating the same

Publication Date: 2023.04.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An electrostatic discharge (ESD) protection circuit includes a first diode, a second diode and an ESD clamp circuit. The first diode is in a semiconductor wafer, and is coupled to an input output (IO) pad. The second diode is in the semiconductor wafer, and is coupled to the first diode and the TO pad. The ESD clamp circuit is in the semiconductor wafer, and is coupled to the first diode and the second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer. The first signal tap region is coupled to a first voltage supply. The first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit.