Semiconductor ESD Protection Circuit with Segmented Sub-Circuit
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Solution Overview
Problem
In semiconductor devices with multiple power source systems integrated on a single chip, the existing ESD protection configurations can lead to high stress voltages between the gates and sources of transistors, increasing the risk of transistor breakdown, particularly due to the miniaturization of MOS transistors which reduces breakdown voltage but not the operational voltage of ESD protection elements.
Innovation Solution
The implementation of a semiconductor device with a main protection circuit unit and a sub protection circuit unit, where the sub protection circuit includes a PMOS transistor or NMOS transistor connected in a way that functions as a resistive element and a sub ESD protection element to reduce stress voltages applied to transistors during ESD events, providing additional discharge routes and operating at lower voltages to mitigate transistor breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection elements are connected between power source pads and ground pads in multiple power source systems, then the internal circuit is protected from ESD surge, but high stress voltages are applied between gates and sources of transistors, increasing the risk of transistor breakdown
Solution Approach 1:
The ESD protection function is divided into two separate circuit units: a main protection circuit unit connected between power source pads and ground pads, and a sub protection circuit unit connected between signal lines and ground lines. This segmentation allows the main unit to handle high-voltage ESD surges while the sub unit specifically protects transistors by providing alternative discharge paths, thereby reducing stress voltages on transistor gates and sources.
Solution Approach 2:
The sub protection circuit unit acts as an intermediary between the main protection circuit and the input circuit transistors. When ESD surges occur, the sub protection circuit provides additional discharge routes through its PMOS/NMOS transistors connected to ground, mediating the voltage stress and preventing direct application of high voltages to the input circuit transistors, thus protecting them from breakdown.
2Productivity
If MOS transistors are miniaturized to reduce device size, then integration density is improved, but breakdown voltage of transistors is reduced, making them more susceptible to ESD damage
Solution Approach 1:
The sub protection circuit unit is pre-configured with PMOS and NMOS transistors connected between signal lines and ground lines, creating a protective buffer before ESD surges can reach the miniaturized transistors. This prior cushioning structure provides alternative low-impedance discharge paths that become active during ESD events, protecting the vulnerable miniaturized transistors from voltage breakdown while allowing continued high-density integration.
3Reliability
If a main protection circuit unit is implemented to provide discharge routes between power source pads and ground lines, then ESD protection is improved, but additional sub protection circuitry is needed to fully protect input circuits, increasing device complexity
Solution Approach 1:
The sub protection circuit unit merges multiple protective functions into a single compact structure: it provides discharge routes for ESD surges, clamps voltage on signal lines, and protects input circuit transistors simultaneously. By combining these functions in one integrated unit with PMOS and NMOS transistors sharing common ground connections, the design achieves comprehensive protection without proportionally increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the breakdown of input circuits caused by ESD surge voltages by providing additional discharge routes and reducing stress voltages applied to transistors, thereby protecting NMOS and PMOS transistors from damage.
Implementation Method 1
The off transistor implies a MOS transistor in which a potential of a gate is fixed such that the transistor is turned off at the time of the usual operation. Then, the ESD surge is discharged by a parasitic bipolar operation.
Implementation Method 2
an ESD protection element is connected between the power source pad and the ground pad in a pair of the power source pad and the ground pad, respectively. Thus, the internal circuit is protected from the ESD surge.
Data Source
AI summary
A semiconductor device includes: a first power source (PS1) pad supplied with a PS1 voltage; a PS1 line connected to the PS1 pad; a first ground line (G1); an output circuit operated using the PS1 voltage; a second power source (PS2) pad supplied with a PS2 voltage; a PS2 line connected to the PS2 pad; a second ground line (G2); a signal line connected to an output end of the output circuit; an input circuit connected to the signal line at an input end receiving a signal from the output end and operated using the PS2 voltage; a main protection circuit unit providing discharge routes between the PS1 pad and G1, G1 and G2, and G2 and the PS2 pad; and a sub protection circuit unit. The output circuit includes: a circuit element arranged between the PS1 line and the signal line and able to function as a resistive element.