ESD Protection Circuit for Display Panels Using TFT Segmentation
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Solution Overview
Problem
Existing ESD protection circuits for display panels, particularly those using depletion-type TFTs, suffer from significant leakage current issues during normal operation, which can damage pixel units and peripheral circuits due to the depletion-type TFTs being turned on regardless of voltage polarity, leading to abnormal operation and potential damage.
Innovation Solution
An ESD protection circuit comprising four TFTs and a bootstrap capacitor, where the first and fourth TFTs are turned on during normal operation to minimize current and voltage impact, and the second and third TFTs are activated during ESD events to quickly discharge charges to the power supply lines, ensuring low power consumption and effective protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If depletion-type TFTs are used in ESD protection circuits, then ESD discharge capability is improved, but leakage current during normal operation increases significantly
Solution Approach 1:
The ESD protection circuit is divided into multiple TFTs (first TFT, second TFT, third TFT, fourth TFT) with distinct functions. The first and fourth TFTs handle normal operation with minimal leakage, while the second and third TFTs are specifically activated during ESD events, segmenting the protection mechanism to resolve the contradiction between ESD capability and leakage current.
Solution Approach 2:
The circuit dynamically switches between different TFT configurations based on operating conditions. During normal operation, only the first and fourth TFTs are turned on with low current. During ESD events, the circuit dynamically activates the second and third TFTs to provide rapid charge discharge, enabling adaptive response to different operational states.
2Device complexity
If simple ESD protection structures are used, then device complexity is reduced, but forward current during normal operation damages pixel circuits
Solution Approach 1:
The fourth TFT acts as an intermediary element that controls the activation of the ESD protection path. During normal operation, it maintains a controlled state that prevents excessive forward current while still enabling rapid response during ESD events, serving as a mediator between the data signal line and the protection mechanism.
Solution Approach 2:
The circuit changes its electrical parameters dynamically based on operating conditions. During normal operation, the circuit maintains high impedance to prevent forward current. During ESD events, it transitions to low impedance state for rapid charge discharge, achieving parameter changes that resolve the contradiction between simplicity and protection effectiveness.
3Reliability
If ESD charges are discharged quickly to power supply lines, then ESD protection effectiveness is improved, but power consumption increases during normal operation
Solution Approach 1:
The circuit operates in periodic states: during normal operation, only the first and fourth TFTs are active with minimal current consumption. During ESD events, the second and third TFTs are activated for rapid charge discharge. This periodic activation pattern enables fast ESD response while maintaining low power consumption during normal operation.
Solution Approach 2:
The ESD discharge function is extracted as a separate, independently controllable mechanism from the normal operation path. The second and third TFTs are specifically dedicated to ESD discharge and are only activated when needed, separating the ESD protection function from the normal signal path to avoid continuous power consumption.
Data Source
AI summary
The invention discloses an ESD protection circuit and a method for driving the same and a display panel. The ESD protection circuit in the present invention comprises: a first TFT with a drain connected to a data signal line, a source and a gate connected together as a node; a second TFT with a drain connected to a first power supply line, a source connected to the data signal line, and a gate connected to the node; a third TFT with a drain connected to the data signal line, a source connected to a second power supply line, and a gate connected to a third power supply line; a forth TFT with a drain connected to the node, a source and a gate connected to the second power supply line; and a bootstrap capacitor connected between the node and the data signal line.