ESD Protection Using Third Well and Transient Voltage Source
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Solution Overview
Problem
High Voltage BCD technologies are prone to circuit failure due to turn-on of parasitic transistors during electrostatic discharge events, leading to overheating, silicon filamentation, and structural damage.
Innovation Solution
Incorporating a third well with opposite doping type and a transient voltage source connected to it, which provides a voltage less than the clamp voltage during an ESD event, to prevent parasitic transistor turn-on and reduce energy release at the collector junction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power clamps are used to protect circuits from overvoltage during ESD events, then circuit protection is improved, but parasitic transistor turn-on still occurs causing overheating and device failure
Solution Approach 1:
A third well (intermediary structure) is introduced between the first and second wells. This third well acts as a mediator that collects electrons during ESD events, preventing direct electron flow that would cause parasitic transistor turn-on. The transient voltage source connected to the third well maintains it at a potential less than the clamp voltage, enabling it to intercept electrons before they reach the parasitic transistor junction.
Solution Approach 2:
The patent changes the voltage parameter distribution during ESD events by introducing a transient voltage source connected to the third well. This voltage source dynamically adjusts the potential of the third well to be less than the clamp voltage but greater than the substrate potential, creating a controlled electric field that redirects electron flow and prevents harmful parasitic transistor activation.
2Adaptability or versatility
If high voltage BCD technology is used to integrate bipolar and CMOS transistors, then device functionality is improved, but susceptibility to ESD damage increases
Solution Approach 1:
The protection mechanism is segmented into three separate wells (first, second, and third wells) with distinct functions. The first and second wells are connected to external terminals for normal operation, while the third well is specifically dedicated to ESD protection by collecting electrons during discharge events. This segmentation allows the device to maintain high voltage BCD functionality while adding specialized protection without compromising the integrated circuit's versatility.
3Reliability
If ESD clamp voltage is set to protect circuits, then overvoltage protection is improved, but energy release at collector junction increases causing silicon filamentation
Solution Approach 1:
The third well serves as an intermediary electron collection point that intercepts electrons before they reach the collector junction between the first and second wells. By providing this intermediate path, the energy that would otherwise be released as heat at the collector junction is instead dissipated through the third well, significantly reducing the risk of silicon filamentation while maintaining overvoltage protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the risk of parasitic transistor turn-on, prevents overheating and silicon filamentation, and minimizes the potential for device failure by managing electron collection and reducing power dissipation during ESD events.
Implementation Method 1
High Voltage BCD technologies (e.g., with operating voltages in excess of 100V), are prone to a circuit failure due to turn-on of a parasitic transistor between wells during an electrostatic discharge event (ESD) event
Data Source
AI summary
In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.