ESD Protection Device With Three-Terminal Substrate
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Solution Overview
Problem
Existing ESD protection devices with zener diodes suffer from increased ESL and impaired signal transmission characteristics due to the series connection of ESL with wiring lines, degrading both ESD protection performance and signal transmission.
Innovation Solution
An ESD protection device with a semiconductor substrate having a rectangular cuboid shape, featuring a wiring electrode and a third terminal electrode connected to ground, which reduces ESL by shortening the current path and increasing the sectional area, along with a re-wiring layer that minimizes distances between electrodes, thereby reducing wiring resistance and parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional two-terminal zener diode structure is used, then ESD protection function is provided, but ESL increases due to series connection with wiring lines
Solution Approach 1:
The patent transitions from a planar two-terminal structure to a three-terminal structure with electrodes arranged in different spatial dimensions. The first and second terminal electrodes are positioned at opposite ends of the semiconductor substrate while the third terminal electrode is positioned at the center, creating a three-dimensional current path configuration that reduces ESL by eliminating series connection with external wiring lines.
Solution Approach 2:
The patent divides the current path into multiple segments by introducing a third terminal electrode at the center of the semiconductor substrate. This segmentation allows the current to flow through multiple parallel paths (first semiconductor region and second semiconductor region) rather than a single series path, thereby reducing the overall ESL while maintaining ESD protection functionality.
2Ease of operation
If wiring lines connect the TVS element to outer connection electrodes, then electrical connection is established, but transmission characteristics of desired signal are degraded
Solution Approach 1:
The patent merges the function of external wiring lines with the semiconductor substrate itself by forming terminal electrodes directly on the substrate surface. The wiring lines are substantially embedded in the semiconductor substrate, eliminating the need for separate external connection wires and reducing parasitic inductance that degrades signal transmission characteristics.
Solution Approach 2:
The patent extracts and eliminates the harmful wiring lines from the current path by integrating all necessary electrical connections directly into the semiconductor substrate structure. The terminal electrodes are formed on the substrate surface and connected through internal semiconductor regions, removing the source of ESL and signal degradation from the system.
3Reliability
If current path length is increased to connect electrodes, then electrical connection is achieved, but ESL and resistance increase
Solution Approach 1:
The patent employs an asymmetric electrode arrangement where the third terminal electrode is positioned at the center of the semiconductor substrate while the first and second terminal electrodes are positioned at opposite ends. This asymmetric configuration creates optimized current flow paths that minimize total path length and reduce both ESL and resistance by leveraging the geometric properties of the substrate.
Solution Approach 2:
The patent optimizes the local electrical properties by positioning the third terminal electrode at the center of the semiconductor substrate, creating a configuration where the current path length and resistance are minimized in the critical connection regions. The local electrode density and arrangement are optimized to reduce parasitic effects while maintaining overall connection reliability.
Data Source
AI summary
An ESD protection device that includes a semiconductor substrate that has a first main surface, terminal electrodes formed on the first main surface, a terminal electrode that is connected to the ground, and a wiring electrode that connects the terminal electrodes to each other and that forms a part of a main line. Moreover, the semiconductor substrate has a rectangular cuboid shape in a plan view and further includes a first semiconductor region that is connected to the wiring electrode, a second semiconductor region that is connected to the third terminal electrode, and a third semiconductor region. The first semiconductor region and the second semiconductor region are arranged along short sides of the semiconductor substrate and electrically connected to each other with the third semiconductor region that extends along the short sides interposed therebetween.